Joe Baylon, Md Aminul Hoque, Deukhyoun Heo
©SHUTTERSTOCK.COM/CIFOTART
The millimeter-wave (mm-wave) frequency range is consumer wireless technology’s next frontier. Next-generation cellular technologies demand ever-increasing data rates, reduced latency, and robust service for a massive number of users. The mm-wave wireless systems operating in the frequency range from 10 to 100 GHz have the potential to satisfy the requirements presented by these consumer demands [1]. High carrier frequencies offer increased communication bandwidths for improved throughput with relatively small fractional bandwidths. Furthermore, because the development of mm-wave wireless and cellular technologies is in its infancy, relatively few external interferers exist at these frequencies. Thanks to the continued scaling of CMOS devices and increased transit and maximum frequencies, the integration of high-performance mm-wave transceivers is more viable than ever before. Transceiver integration further benefits from the decreased size of passive devices with high-frequency operation, decreasing silicon area and minimizing parasitic effects. Thanks to these benefits, 5G hardware research has focused on exploring limitations and establishing design principles for integrated CMOS mm-wave front ends.
Despite the advances in hardware design in recent years, specification of the 5G wireless standard is still a work in progress, particularly for the so-called high-band (HB) 5G spectrum extended across mm-wave frequencies. The Federal Communications Commission has already allocated 5G frequency bands up to 42 GHz with expectations to extend 5G HB frequency allocations to 95 GHz [2]. The demand for high-speed, reliable service for an ever-growing customer base will clearly continue to increase, and with it standards and systems must evolve (and indeed are already evolving [3]) to take advantage of the wide bandwidths available across mm-wave frequency bands (Figure 1). These developments present a difficult challenge for wireless hardware designers. Integrated wireless devices must advance to allow robust access to a wide range of mm-wave frequencies [3].
Figure 1. Industry leaders in wireless and cellular technologies have begun exploring standards and the requisite hardware for 5G NR. NR: New Radio. (Source: Qualcomm [3].)
The potential for frequency-agile and standard agile transceivers extends far beyond the future of 5G. Modern smartphones support numerous wireless standards: LTE, code-division multiple access, and other legacy cellular systems; dual-band Wi-Fi; Bluetooth; various GPS protocols; and near-field communication—to name the most prominent. Furthermore, expansion of widely used wireless services into the mm-wave frequency regime is already underway. The standards being developed for next-generation cellular propose mm-wave communication in the Ka-band, which supports huge data rates and robust service for a huge number of users. The newly established wireless Internet standard extends further into the mm-wave regime, making use of the Industry, Science, Medicine band at 60 GHz. A single-chip solution capable of replacing individual transceivers is extremely desirable: it would simplify top-level hardware design, reduce form factor, save power, and reduce the cost of next-generation consumer hardware. However, such a design presents many challenges that demand the development of improved technologies and design techniques. Of course, these challenges are compounded when expansion into the mm-wave regimes of 5G cellular (Ka-band) and WiGig (V-band) is considered.
These technologies require significant innovations in transceiver hardware technologies for mm-wave frequencies. Each block in frequency-agile, multiband mm-wave transceivers will need to leverage wideband and band-switchable architectures to enable top-level frequency agility. However, we will focus on wideband and multiband signal generation. Generation of local oscillator (LO) signals is critical for upconversion and downconversion in a mm-wave transceiver, and integration of high-performance low-power oscillators for mm-wave systems remains a difficult design challenge. Maintaining low LO phase noise is critical to ensure adequate modulation purity and demodulation accuracy [4], [5]. Furthermore, keeping the power consumption as low as possible enables wireless applications for burgeoning high-data-rate standards. We will discuss state-of-the-art wideband signal source topologies designed to address these challenges.
Numerous circuit and topological innovations have been targeted at supplying wideband, multistandard signal sources. For low-frequency wideband signal generation, the most common technique is to generate a harmonic of the desired frequency and convert this harmonic down to the desired frequency range. This fundamental tone is then divided by a digitally controllable frequency divider with several programmable division ratios. This division, paired with acceptable tunability of the fundamental oscillator, can achieve very wide fractional tuning range (FTR) with relatively low power consumption [6], [7]. However, digitally programmable dividers are somewhat complex to design, and the limitations of digital frequency dividers dictate a relatively low maximum frequency of operation for the oscillator. This topology, while useful at low frequencies, cannot address the need for wideband and multiband signal sources in the mm-wave frequency regime.
High-frequency options for wideband and multiband signal source design should therefore be explored. Unfortunately, this problem becomes increasingly difficult at mm-wave frequencies. Because the inductance and capacitance values of a parallel LC resonant tank, as shown in Figure 2, are smaller for higher frequency resonance, parasitic inductance and capacitance have a proportionately increased effect on the tank impedance. Modern integrated LC voltage-controlled oscillators (VCOs) or digitally controlled oscillators (DCOs) are tuned solely using variable capacitances resonating with a fixed inductance. Parasitic capacitances from active and passive devices therefore have a particularly outsized effect on the mm-wave oscillator tuning range. As shown in (1), the FTR of a capacitively tuned VCO is a function of the ratio of the maximum to minimum capacitance ${\eta}{.}$ With ${\eta}$ ranging from one ${(}{C}_{\max} = {C}_{\min},$ indicating no tunability) to $\infty{(}{C}_{\min} = {0}{),}$ the FTR ranges from 0 to 2. At mm-wave frequencies, ${\eta}$ often falls between 1.25 and 1.5, including device and interconnect parasitic capacitance, giving a tuning FTR maximum of 20% (and often much less). While this tuning range is sufficient to compensate for process, voltage, and temperature (PVT) drift, it cannot accommodate multiband or multistandard frequency generation. Furthermore, even a 20% FTR involves compromising the oscillator’s performance by degrading the quality factor of the capacitors. To simultaneously expand the FTR of mm-wave signal source circuits and maintain or improve the signal source performance, innovative alternatives must be explored. \[{FTR} = \frac{\Delta{f}}{{f}_{c}} = {2}\ast\left({\frac{\sqrt{{C}_{\max}}{-}\sqrt{{C}_{\min}}}{\sqrt{{C}_{\max}} + \sqrt{{C}_{\min}}}}\right) = \frac{{2}\left({\sqrt{\eta}{-}{1}}\right)}{\sqrt{\eta} + {1}}{.} \tag{1} \]
Figure 2. Capacitively tuned parallel resonant tank, typically used in LC oscillator designs.
Wideband signal sources in the mm-wave regime often focus on harmonic generation, essentially the antithesis of subharmonic generation using programmable frequency dividers. In this topology, a fundamental oscillator is designed well below the desired frequency of operation. This oscillator leverages the advantages of low-frequency oscillator designs, namely lower power consumption, low phase noise, and relatively low parasitic capacitance. To generate the desired frequency tones, this signal is then multiplied through various methods [8], [9], [10], [11]. The phase noise of the resulting harmonic tones is degraded by a factor of ${20}\ast\log{N},$ where N is the frequency multiplication factor. It should be noted, however, that fundamental oscillators at higher frequencies usually suffer from higher noise caused by the degraded tank quality factor and degraded active device performance. As a result, harmonic generation often yields improved phase noise performance for a given power consumption compared to the use of fundamental oscillators [12]. However, each stage of multiplication often requires active upconversion mixers and buffers to compensate lossy harmonic generation [11], nullifying much of the power consumption improvement and increasing the design complexity of the signal source circuit. The primary benefit of this harmonic generation technique lies in the FTR of the harmonic tones, which remains identical to that of the wideband, low-frequency fundamental oscillator. Furthermore, the decreased dependence on parasitic capacitances gives a greater robustness to PVT variations.
While the use of harmonic signal generation offers some promising performance benefits, it also suffers from several similar drawbacks to that of the divider-based architecture. The increased design complexity and power consumption make alternatives an appealing area of research. For the remainder of this article, we will discuss several innovations that aim to achieve extremely wideband signal generation while avoiding or improving many of the pitfalls of harmonic generation methods. These innovations pave the way for more compact, lower cost, higher performance signal source circuits that span the mm-wave frequency range. First, we will discuss a harmonic generation circuit that modifies the traditional paradigm by enabling simultaneous availability of three distinct harmonically related sinusoids with an energy-efficient generation architecture. Circuit innovations are introduced that ensure high energy efficiency and low area overhead without compromising signal quality. By generating the fundamental, second, and third harmonics simultaneously, multiband operation across an enormous frequency range can be accomplished by selecting the appropriate harmonic.
The second and third innovations we will discuss entail pushing beyond the traditional limits imposed by the capacitance tuning ratio ${\eta}$ by introducing innovative, low-loss inductive tuning, as shown in Figure 3. Traditionally, tunable inductance has been dismissed as too lossy and too complex for use in practical signal sources. While capacitive tuning is relatively straightforward, manipulation of magnetic flux in on-chip environments is quite difficult. Because of this, even the most advanced innovations in inductive tuning involve switching between two inductance levels rather than continuous tuning. Figure 3 shows the result of such an architecture on signal source tuning. We will discuss two such switchable inductors and their application to wideband signal source circuits. First, we present the switched substrate-shield inductor (SSI) [13], which offers significant improvement in tuning range over capacitive tuning with minimal parasitic overhead. The SSI uses two secondary magnetically coupled shield coils to allow wide tunability of the primary coil’s equivalent inductance. The resulting tunable inductor is used to design a switchable dual-band VCO with state-of-the-art tuning range and phase noise.
Figure 3. Capacitively and inductively tuned parallel resonant tank. Tuned or switchable inductance can dramatically improve the tuning range.
The last design is a dual-mode inductor [14] that presents different reactive behavior based on the excitation profile of the active circuitry. This technique affords large variations in effective inductance while maintaining a high quality factor and low parasitic influence.
With the combined capabilities of low-power harmonic generation, boosted active capacitor topologies for wide tunability, and multiband capabilities enabled by tunable SSIs, single signal source circuits capable of spanning the broad mm-wave frequency range are within reach.
Traditional efforts at harmonic generation rely on power-hungry, multiblock implementations to upconvert the fundamental oscillator’s output signal. However, thanks to a few simple topological observations, some simplifications can be made to reduce the overhead these architectures traditionally demand. This, combined with circuit-level innovations for low-power operation and high signal source performance, gives a multiband signal source architecture suitable for mm-wave frequency ranges. First, it is well known that a differential oscillator topology exhibits a common-mode current draw characterized by the second harmonic of the frequency of oscillation. This presents a compelling opportunity: the second harmonic sinusoid can be freely generated with little or no added power consumption if this common-mode current can be properly leveraged. This simple observation motivates the harmonic generation-based wideband oscillator circuit shown in Figure 4. In this circuit, a fundamental VCO operating from 26.5 to 30.5 GHz creates the fundamental oscillation signal. A passive LC resonant tank extracts the 53–61-GHz second harmonic from the common-mode current. A third harmonic output is generated from the fundamental and second harmonics, using a modified Gilbert cell mixer topology designed for low-power operation, giving a 79.5–91.5-GHz tone.
Figure 4. The triple-band signal source consists of a fundamental VCO, a passive frequency doubler, and a third harmonic modified Gilbert cell mixer. Each subcircuit is designed to optimize performance under low voltage overhead. (Source: [12].)
A signal source based on this architecture is proposed in [12]. The schematic of this circuit is shown in Figure 4. Each block is designed to operate under low power supply voltages, allowing a current reuse topology for low power consumption. The fundamental VCO consumes only the headroom of a single cross-coupled pair. Second harmonic generation is accomplished using a parallel LC tank, which ideally experiences no dc voltage drop and consumes only the power lost to the parasitic equivalent tank resistance. The modified Gilbert cell mixer used for third harmonic generation relies on magnetic coupling between the second harmonic output buffer and the fundamental oscillator, reducing the mixer’s voltage overhead dramatically. Combined, this gives only two transistors stacked between power and the supply voltage. The nominal 1-V supply for a 65-nm CMOS process is more than adequate for such an architecture.
To ensure that generation of the second and third harmonics is efficient and results in usable output power levels, the fundamental oscillator must generate a large output voltage swing. This desire traditionally conflicts with the aforementioned goals of low power consumption and simple, compact architecture. Positive transformer feedback [15] is employed to allow exceptionally low supply voltage operation while maintaining a high output swing. From Figure 4, the introduction of coupling between L 1 and L 2 reinforces the negative transconductance supplied by M 1 and M 2. With appropriate design, the signal at the source nodes of the core transistors will swing out of phase with the gates. This results in an effective Gm boost, which reduces the dc current required to satisfy the start-up conditions. It is worth noting that the presence of L 2 allows the source nodes to swing above and below the dc voltage of the source nodes, increasing the achievable swing for a given dc supply voltage.
With sufficient swing under low power consumption achieved from the fundamental oscillator, passive extraction of the second harmonic signal from the common-mode current is possible. A parallel resonant tank, comprising L 3 and the gate-source capacitance of M 7, is added below the center tap node of L 2. This tank, tuned to resonate at twice the fundamental frequency, extracts a voltage from the common-mode current, I cm. The resulting voltage is amplified to levels comparable to that of the fundamental using the common-source amplifier formed by M 7 and L 6. The second harmonic resonant tank has the added benefit of improving the phase noise of the fundamental VCO by reducing the second harmonic periodic loading of the core transistors on the resonant tank. Because of the large output swing obtained by the Gm-boosted pair, M 1 and M 2 spend a portion of their “on†time in the triode region. This decreases the impedance looking into the drain nodes of the cross-coupled pair, degrading the noise performance of the oscillator. The addition of a high impedance at 2f 0 reduces this loading effect by increasing the impedance of the cross-coupled pair loading the tank at each maximum and minimum [16].
The third harmonic is upconverted from the first and second harmonics using a modified Gilbert cell mixer. The fundamental VCO output directly drives the gates of M 3 and M 4. To reduce the voltage overhead for the mixer, magnetic coupling between L 5 and L 6 applies the second harmonic signal to the source nodes of M 3 and M 4. This eliminates the need for an additional input MOSFET at the source of M 3 and M 4, reducing the voltage overhead. To improve the gain of this upconversion mixer, a cross-coupled pair (M 5 and M 6) provides a small negative transconductance across the load. Varactor-based tuning allows the peak gain frequency to track with the tuning range of the fundamental oscillator, ensuring minimal conversion gain variation across the tuning range.
Each subblock of this signal source circuit leverages innovations for excellent performance under low power consumption. The result is a triple-band signal source capable of operating under a sub-1-V supply while maintaining excellent spectral purity and wide tunability. The proposed triple-band signal source was fabricated in a bulk 65-nm CMOS process. Figure 5(a) shows a photo of the fabricated circuit. A Keysight PXA N9030A signal source analyzer and external V- and W-band mixers were used to characterize the tuning range, output power, and phase noise performance of the fundamental VCO output and the harmonic output signals.
Figure 5. Phase noise for the fundamental VCO, second harmonic, and upconverted third harmonic. The fundamental signal source exhibits phase noise at 1-MHz offset of –121 dBc/Hz. The doubled and tripled output show agreement with the expected 20*log (N). Ctrl: control. (Source [12].)
Figure 5(b) shows the frequency across the tuning range of the three harmonically related outputs ranging from the Ka- to W-band frequency ranges. Figure 5(c) shows the frequency and power consumption across the tuning range of the fundamental VCO. A 13% FTR, ranging from 26.5 to 30.2 GHz, is demonstrated. The measured output power is approximately –12.5 dBm. This power level, however, ignores the approximately 3-dB cable loss. Additionally, a lossy, inductorless output buffer was used to match the output to 50 Ω. Taking this into account, the –12.5-dBm output power corresponds to an approximately 330-mV amplitude single-ended (or 660-mV differential) sinusoidal signal at the output of the VCO. The transformer Gm-boosted topology allows a large output swing, even at a less than 0.5-V effective supply voltage. The total power consumption ranges from 7.6 to 8.3 mW. The phase noise performance for the three frequency bands at 26.5 GHz is shown in Figure 5(d). At 10 MHz, the measured phase noise for the fundamental VCO is –121 dBc/Hz, demonstrating state-of-the-art performance with minimal power overhead.
Harmonic generation is a viable technology to afford multiple-octave frequency generation in a single signal source block. However, this architecture only allows signal generation in discrete, harmonically related frequency bands. If the continuous tunability of the fundamental oscillator can be extended to an octave range, e.g., from 20 to 40 GHz, the harmonically related bands will overlap, allowing continuous frequency generation across all three harmonics. This is quite simply beyond the capabilities of capacitive tuning in its current form. Thankfully, recent publications have begun exploring inductive tuning, designed to extend the tunability of resonant tanks beyond the capabilities of capacitive tuning.
We will discuss two tunable inductor topologies. Both topologies develop innovative methods to alter effective inductance without the use of signal-path switches [17], which would severely degrade the quality factor of the inductor. The first, published in IEEE Transactions on Microwave Theory and Techniques in 2017, leverages mode switching in an innovative inductor topology to achieve octave tuning across a continuous frequency range [14]. An innovative series resonator was proposed that allows dramatically increasing the tuning range controlled by activating and deactivating the active Gm cells in the oscillator core. This allows controlled excitation of the four-port resonator, activating distinct oscillation modes of the structure.
The equivalent schematic representation of the proposed resonator is shown in Figure 6, while the layout and excitation profile are shown in Figure 7. The resonator consists of two inductors connected in series. The three-port configuration gives two available modes, selected by activating the relevant Gm cell, “HB†and “low band†(LB). In the HB mode, each of the two inductors experiences a differential voltage, presenting an inductance L to each Gm cell. Each inductor resonates with a distinct capacitance CD . In the LB configuration, only a single differential excitation is applied across the combined effective inductance of the two series inductors, approximately 2*L. This larger inductance resonates with C LB, which gives a much lower resonant frequency than the HB configuration.
Figure 6. The schematic representations of the series mode-switching resonator for both the (a) HB and (b) LB mode configurations are shown. LB: low band. (Source: [14].)
Figure 7. Layout of the series mode-switching resonator discussed from [14]. The polarity and location of the excitation will yield dramatically different effective inductances.
Notably, this inductance variation is achieved without the use of signal-path switches. By controlling the activation of the Gm cells rather than switching inductance values directly, the Q-degrading impact of series switches is avoided. However, substrate losses, resistive losses, and the added complexity of a dual-mode inductor give rise to dramatic impedance variations across the resonator’s tuning range. Wide traces improve the quality factor at low frequencies due to a corresponding reduction in resistive losses. By contrast, at high frequencies, substrate losses begin to dominate, degrading the quality factor.
As Figure 7 shows, a two-wire approach was used to improve this tradeoff, effectively changing the conductor’s width by leveraging the signal polarities in each mode. In the HB mode, ports 1 and 4 experience the same polarity signal, while ports 2 and 3 are excited out of phase from 1 and 4. Because the midpoint of the outer coil is not connected to ports 2 and 3, no differential voltage is applied across sections of the outer coil. The inductor’s conductive path is therefore limited to the inner coils, limiting substrate coupling and improving the Q at high frequencies. In the LB configuration, ports 1 and 4 are excited differentially, while the inner ports (2 and 3) are left open. The outer and inner coils therefore experience the same excitation, giving rise to a wider conductive path and improved Q at low frequencies.
A wideband, dual-mode oscillator was designed using this innovative resonator, and it spans 6.4–14 GHz. The oscillator uses single-stack NMOS cross-coupled pairs for the core transconductance cells. These cells are activated and deactivated using switches between these cells and ground and additional enable switches from the center tap points of the inductor to V DD. While the VCO achieves a good figure of merit (FoM) of –186 dBc/Hz and consumes relatively little power (less than 10.3 mW), the FTR is where it truly shines. Figure 8 shows the oscillation frequency versus the digital control word for both frequency band configurations. The LB covers the frequency range from 6.39 to 8.9 GHz, and the HB ranges from 8.38 to 14 GHz. Note that, with some overlap, this oscillator spans an FTR of 74.6%, extending well beyond an octave tuning range.
Figure 8. Oscillation frequency versus control word in both the LB and HB configurations. (Source: [14].) Sim: simulated.
This resonator design exhibits the immense benefit afforded by developing tunable or multimode inductance values for multiband oscillator design. Although this resonator design is limited to multimode operation—that is, the inductance is controlled between a set of distinct values—pairing this innovation with capacitive tuning allows for continuous coverage across a large tuning range. Continued innovation in tunable inductor design, however, must be pursued. To improve the quality factor for high performance, a low power oscillator design is necessary. Compact size is also highly desirable to maximize the benefit of integrating multiband or multistandard oscillators in a single block. While this is just a single example of a growing body of research investigating tunable or multimode inductors, it provides an excellent example of the potential benefits of inductive tuning for multiband designs.
The series resonance mode inductor discussed previously exemplifies one type of inductively tuned oscillator topologies explored in recent work. While innovative multimode resonators with various sophisticated resonance schemes offer significant jumps in oscillator tunability compared to capacitively tuned designs, these resonators also present a new set of restrictions imposed by the sophisticated excitation methods and complex passive component layout. Alternative approaches that offer similar benefits of high quality factor and low area overhead without introducing these additional restrictions are therefore eminently desirable.
Switched transformer inductors [18], [19] have been proposed that offer many of these benefits but avoid the additional restrictions. Concentric coils are simple to design and offer a relatively large coupling factor, enabling wide tunability. The secondary coil is commonly implemented using a thick metal layer, usually in the same or an immediately neighboring metal layer, to maximize the ${Q}_{S}$ and maintain a large coupling factor. A low-resistivity secondary coil layer also minimizes the substrate losses by absorbing the tangential electromagnetic fields. However, a large parasitic coupling capacitance exists between the primary coil and the secondary coil because of a small vertical gap between the metal layers of the primary and secondary coils. There are, however, alternatives to the topologies typically used. If a lower metal layer is selected, the vertical distance can be greatly increased, reducing the coupling capacitance dramatically. This improvement comes at an obvious cost: lower layers sacrifice the low sheet resistance of the thicker metal layers near the top of the stack-up. However, changes in the quality factor of the secondary coil have a minimal influence on the inductive tunability of the primary coil, indicating the potential usefulness of such an approach.
In [13], an SSI has been proposed that makes use of the reduced parasitic effects of implementing the secondary coil in lower metal layers. The layout of the proposed SSI is shown in Figure 9. Unlike conventional designs [18], [19], the secondary coil is formed around a floating shield in the lowest metal layer M 1. In the SSI, the shield serves to terminate capacitive coupling, reducing substrate losses. A thin metal shield layer also minimizes induction losses due to the tangential H-field by directly shielding from substrate coupling. This design uses only two layers to ensure minimum intercoil parasitic capacitance and to avoid higher order resonance modes.
Figure 9. The top view of the SSI layout. When Vsw is high, current flows in the two substrate coils. (Source: [13].)
As in traditional switched transformer designs, a secondary coil is configured with a switch that allows or disallows current in the secondary coil. When the switch is in the “on†state, current is conducted in the secondary coil, allowing the generation of an opposing magnetic field through the primary coil, reducing the effective inductance. In the “off†state, the switch exhibits high impedance, effectively limiting the current to 0. In this state, no opposing magnetic field is generated, so the inductor exhibits its maximum value. Care is taken in the layout of the smaller traces of the shield to ensure minimal magnetic coupling, so the rest of the substrate shield in which the coil is embedded exhibits identical behavior in the “on†and “off†states.
A prototype of the proposed SSI with two substrate-shield secondary coils (SSI2) for increased magnetic coupling and larger tuning range was fabricated and measured in 65-nm CMOS. A chip photograph of the fabricated inductor is shown in Figure 10(a). As shown in Figure 10(b), the inductance (observed at 30 GHz) can be switched between approximately 140 and 195 pH, giving a 40% inductance tuning range. The quality factor, shown in Figure 10(c), ranges from 10 to 23 at 30 GHz. While some Q degradation is observed, as expected, when the MOSFET switch is configured in the “on†state, the excellent tuning range and compact layout offer excellent benefits for wideband oscillator design. A reduced resonator Q may increase the LO phase noise under the “on†state condition. Alternatively, an increased LO power budget can counteract the LO noise increase, should the system’s power budget permit. However, note that even in the “on†state, the quality factor of the SSI is sufficient for high-performance oscillators suitable for many wideband or multiprotocol applications. To demonstrate the capabilities of this SSI design, a widely tunable oscillator was designed in 65-nm CMOS technology. A schematic of this oscillator is shown in Figure 11. An accumulation-mode varactor provides continuous frequency tuning, while the SSI allows for discrete frequency-band switching. The core Gm cell is a cross-coupled CMOS architecture, giving large negative transconductance under modest power consumption. M Tail provides the fixed dc current.
Figure 10. (a) The chip micrograph of the SSI2. (b) The simulated and measured equivalent inductance across the switch’s control voltage, VSW. (c) The quality factor across VSW. Meas.: measured; Sim.: simulated. (Source: [13].)
Figure 11. The SSI–VCO schematic uses a CMOS inverter-based Gm cell with a tail current source, MTail. (Source: [13].)
A chip micrograph of the SSI–VCO is shown in Figure 12(a). The VCO core draws 4.3 ± 0.2 mA current from a 1-V supply. Figure 12(b) shows the frequency of oscillation across the tuning voltage for both the LB (off) and HB (on) settings of the SSI2. The oscillator achieves a large FTR of 40.3%, including 21–26.3 GHz in the “off†state and 23.6–31.6 GHz in the “on†state. The SSI–VCO has a measured and simulated TR of 40.3% and 42.3%, respectively. It is worth noting that the two states overlap by 2.7 GHz or nearly 10% FTR. While this overlap is intended to ensure continuous tuning in the presence of PVT variations, careful calibration and tuning to account for these would offer an even larger tuning range.
Figure 12. (a) The SSI2–VCO chip micrograph. The 50 Ω on-chip termination for one differential output is labeled “50 Ω Term.†(b) The tuning range across the varactor control voltage for the LB (VSW = 0) and HB (VSW = 1). (Source: [13].)
The tuning range of this SSI-based oscillator is high compared to capacitively tuned oscillators but is notably smaller than the tuning range of the multimode oscillator discussed previously. This is a result of the design tradeoffs of the two resonator designs. The SSI design results in very little additional design overhead, requiring only one additional MOSFET switch for selection of the frequency band. Additionally, the SSI oscillator occupies a very small area overhead because of the simple, compact layout of the single inductor in the resonator. While the SSI resonator does compromise the quality factor in the “on†state, i.e., low inductance settings, the performance cost is manageable. The prototype oscillator boasts a measured FoM as high as 183 dBc/Hz. It should be noted that, for some applications, lower phase noise or reduced power consumption may be required, prompting a need for resonators with a higher quality factor across frequency. This may motivate the adoption of more complex oscillator control schemes that could offer further improvement in high-performance oscillator tunability at the cost of design complexity and chip area.
An attractive solution for generating multiband oscillation in the mm-wave region could be utilized by the dual-path phase-switched inductor, first presented in [20], for widely separated multiband operation in the Ka-band. In addition to using switch-based digital capacitor banks to enable intraband frequency tunability, a novel polarity-based tunable inductor is presented here. Based on the input polarity of the differential signal applied to the four-port inductor, two different inductance values are presented to the resonator, which enables coarse frequency tuning, or dual-band oscillation. Since this mode of operation does not require a series switch in the signal path, a high quality factor is ensured in both modes of operation.
The tunable inductance is achieved by controlling the relative phases of the two differential ports of the inductor, which alters the signal path through the inductor, as shown in Figure 13(a). When the two inputs are out of phase (odd mode), as in Figure 13(a) (left), the signal path passes from the positive node of the left input to the negative node of the right, passing only through the respective loops on the top and bottom of the inductor. However, if the polarity of the right input is switched, giving in-phase (even mode) inputs, the return path passes through the long center trace connecting the top and bottom loops, as in Figure 13(a) (right), increasing the effective inductance between the excitation ports significantly. The simulated inductance values in the two modes are shown in Figure 13(b) (top). As can be seen, there is an increase of about 90% in the inductance value. The quality factor remains greater than 20 for a wide range of frequencies. For demonstration, a dual-band DCO is presented in [20]. The schematic of the DCO is shown in Figure 14, with the dual-path inductor represented as a four-port inductor. The DCO shows excellent phase noise performance with only 4.8-mW power consumption. The FTR is greater than 20% with the center frequencies located at 16.75 GHz and 23.7 GHz. As a result, the DCO shows a very good FoM of 187 dBc/Hz and an FoM with tuning range of 195 dBc/Hz.
Figure 13. (a) The dual-path phase-switched inductor is shown for two modes (odd mode excitation shown in left figure and even mode excitation shown in right figure). (b) Top figure shows simulated inductance values in the two modes of operation; bottom figure shows simulated quality factor. (Source: [20].)
Figure 14. Schematic of the proposed DCO with the dual-path inductor and two NMOS active cores. (Source: [20].)
The proposed inductor presented in [20] could present a ratio of 1.9:1 for the change in inductance in the two modes, because of its physical shape. An improved design is presented in [21], where the change in inductance is increased to 4:1. By using this enhanced change in inductance, an octave frequency range low-phase noise VCO is demonstrated. The physical structure of the inductor is shown in Figure 15. The operational principle is similar to that of the dual-path inductor in [20]. However, instead of a center trace, the inductor is formed by the outer loop in the even mode. As a result, a much larger inductance can be achieved in even mode, increasing the change of inductance ratio up to 4:1. The proposed inductor structure and its even/odd mode operation are shown in Figure 16(a) and (b). Since there is no physical limitation imposed on the outer loop diameter, it can be enlarged as needed. For demonstration purpose, 4× variation in the inductance value was implemented in 65-nm CMOS. Figure 16 (c) and (d) shows the inductance values and quality factor in the two modes. Additionally, a mode-switching capacitor is added to enable triple-band oscillation. The proposed triple-band VCO achieves oscillation centered at 19, 28, and 36 GHz. The bandwidth at each band is about 3 GHz, which is enough to cover the 5G standard. Due to the excellent quality factor of the inductor and the use of a smaller size of the capacitor bank and varactor, the VCO achieves good phase noise and low power consumption in three distinct bands. The triple-band VCO consumes only 2.4–4.7 mW dc power and has excellent phase noise, resulting in excellent FoM in the K/Ka-band.
Figure 15. The dual-path phase-switched inductor is shown for two modes: (a) even mode excitation and (b) odd mode excitation. (c) Simulated inductance values in the two modes of operation. (d) Simulated quality factor. (Source: [21].)
Figure 16. (a) Schematic of the triple-band class-D VCO. (b) Fabricated chip in 65-nm CMOS process. Cap.: capacitor. (Source: [21].)
Several techniques have been discussed that extend the tuning capabilities of integrated VCOs. The summary of these techniques presented here is neither a comprehensive treatment of the ideas nor an exhaustive discussion of the numerous innovations that expand the limits of signal source design. However, these techniques present a unique and unprecedented opportunity for multiband, multistandard integrated transceiver design. For example, if the tunable inductor techniques alongside more traditional capacitively tuned resonators are applied simultaneously to a single K-band oscillator design, an FTR of more than 66% is readily achievable. Notably, a 66% tuning range paired with the triple-band harmonic generation technique or multiband signal generation using dual-path phase-switched inductors discussed previously would allow generation of a sinusoid ranging across an incredibly large continuous frequency span, conceivably ranging from 20 to 100 GHz, in one compact, low-power, high-performance, modular signal source block. The possibilities for such a block are enormous, spanning military, radar, wireless backhaul, mobile, and instrumentation applications. Recently, several articles have presented the idea of mode-switching inductors in leveraging widely separated multiband VCOs in mm-wave, targeting X-band [22], [23], K/Ka-band [20], [21], and V-band [24] operations.
Furthermore, widely tunable resonant tanks and matching networks made possible by multimode inductor designs and SSI innovations can dramatically influence several other mm-wave transceiver blocks. For example, the SSI technique has been used very successfully to design high-efficiency band-switchable power amplifiers (PAs) [25], [26]. Another innovative approach has applied the SSI technique for analog predistortion to improve the linearity in high-efficiency PA design [27]. There are ongoing efforts in utilizing multiport mode-switching inductors with reconfigurable cores to improve phase noise with lower power consumption. Moreover, research work is being conducted using multimode inductors to construct multiband PAs. Continued advancement in these wideband and multiband technologies may well be the key to cheaper, more compact, and more robust transceivers for future generations of wireless communication.
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Digital Object Identifier 10.1109/MMM.2023.3265457
