Qiumeng Wei, Bin Gao, Jianshi Tang, He Qian, Huaqiang Wu
©SHUTTERSTOCK.COM/VLADDON
In this article, we review the development of emerging memory-based neuromorphic computing. First, we discuss the motivation and advantages of this approach. We then summarize the mechanisms and electrical behaviors of commonly used emerging memory devices as well as their application characteristics in various neuromorphic computing paradigms, including computing in memory (CIM) and other biologically plausible brain-like computing. Next, we introduce the principles of CIM and analyze its characteristics from the perspective of parallelism, precision, and signal domains. We also summarize some representative works on chip and system implementations. Additionally, we review the state of the art of other brain-like computing approaches, such as spiking neural networks (SNNs) and reservoir computing (RC). Finally, we provide insights and conclusions on the potential and obstacles of developing neuromorphic computing based on emerging memory, from both the device and system levels.
Since the advent and widespread adoption of backpropagation algorithms in the 1980s, neural networks have undergone exponential growth in both scale and learning capacity. However, the increasing number of parameters required for artificial intelligence (AI) places a heavy burden on computing hardware. For example, the latest GPT-4 model includes more than 100 trillion parameters, approximately 570 times more than that of GPT-3 [1]. Such a massive model, like GPT-3, reportedly requires more than 285,000 CPU cores and 10,000 GPUs for its training, resulting in a power consumption of more than 1,000 MWh. In addition to large models, AI has been extensively used for edge computing applications to reduce response latency and enhance privacy. However, due to the volatility of on-chip memory and integration difficulties with embedded flash in advanced technology nodes [2], achieving favorable energy efficiency, minimal area overhead, and large memory capacity simultaneously has been challenging. In contrast, the human brain can execute more than 1 million trillion operations per second (TOPS) using only 20 W of power and exhibits exceptional memory and learning abilities [3].
In comparison to the binarized information representation, the human brain processes and stores information in analog methods, significantly boosting the storage density and information utilization. In addition, the human brain features an integrated memory–computing architecture, obviating the necessity for frequent data transfer between separate memory and computing units in conventional computing platforms [Figure 1(a)]. Moreover, memory in the brain is represented as analog values, such as continuous synaptic weights, with information delivery taking the form of spike firing, contributing to sparser network activity. Additionally, the brain’s processing exhibits nonlinearity, dynamics, and stochasticity, augmenting its ability to express information [4]. Inspired by the workings of the human brain, neuromorphic computing aims to create systems that emulate the brain at multiple levels, from top-level algorithms to bottom-level units, as shown in Figure 1(b).
Figure 1. (a) Separated memory and computation units in conventional computing systems. (b) Algorithm, circuit, device, and architecture levels to implement neuromorphic computing.
At the algorithm level, a typical approach is to use SNNs [5], which replace artificial neural networks (ANNs) with spike-based information representation and dynamic neurons, resulting in systems that have more temporal information processing ability. Synaptic plasticity-based learning rules are also utilized to train networks without supervision [6], [7]. At the architecture level, on the one hand, in-memory computing is employed to mitigate frequent data transfers. On the other hand, asynchronous event-driven information transferring, with flexible data routing, is realized to mimic the operation of biological neural networks (BioNNs), such as Loihi [8]. At the circuit level, some neuromorphic chips, like Tianji [9], use digital-circuit-based neuron cores, including axons, dendrites, somas, and neuron routers, to construct the system. Other works emulate the neural units in the mixed-signal domain, such as the study on the ROLLS processor [10], which uses exponential I–V characteristics to replicate the behavior of neurons.
Several demonstrations have highlighted the advantages of neuromorphic computing systems in terms of their low-power and high-speed dynamic information processing capabilities [11]. Recently, some studies have implemented neuromorphic computing at the device level, utilizing the specific behaviors of the devices to perform neuromorphic computing functions. Emerging memory, with its high integration density and tunable multilevel states, can efficiently emulate synapses. Additionally, the nonvolatility of certain devices allows for the fusion of computing and memory, without the power consumption or latency associated with data transfer. Based on these features, CIM has been explored for use in emerging device arrays to accelerate large-scale matrix–vector multiplication (MVM) operations. Furthermore, by utilizing emerging memory to emulate dynamic behaviors of synapse plasticity and neuron dynamics, sparse and event-driven network activities and complex neuronal behavior can be realized with lower power and minimal area overheads.
The behaviors of devices are determined by their underlying mechanisms, which in turn influence the suitability of these devices for use in neuromorphic computing systems. Specifically, certain devices are optimized for nonvolatile and analog resistive-switching behaviors, while others with dynamic properties are better suited for constructing artificial neural units. In the following paragraphs, we will summarize various device types along with their corresponding mechanisms and describe the requirements regarding device behavior for high-performance neuromorphic computing systems.
The memristor is an emerging memory device that can modulate its conductance state through programming pulses. It can be classified into nonvolatile and volatile types based on its data retention. Nonvolatile memristor-based arrays, also known as resistive random-access memories (RRAMs), are promising memories with nanosecond-level read latency, picojoule-to-femtojoule-level write power consumption, a footprint of tens of F 2, and the potential for large-scale integration with CMOSs [12]. RRAMs can improve storage density and represent neural network weights by utilizing multilevel resistive states, while volatile memristors exhibiting dynamic behaviors have been utilized in constructing synaptic plasticity and neuronal nonlinear dynamics.
Memristors can be categorized as filament type and interface type, shaped by their working mechanism [13]. Filament-type memristors have two subcategories: cation and anion filament types. The former comprise ions of active metals like Ag and Cu [14], [15], while in the latter, oxygen vacancy is involved [16]. The resistive switching for a filament-type memristor depends on the change in the filament morphology between electrode plates, which can have volatile or nonvolatile behavior depending on the time scale of the ion dynamics. Interfacial memristors depend on the distribution of cations at the interface to modify potential barrier and resistance state. Interfacial memristors offer better analog resistive-switching features than filament-type memristors, but they have a slower write speed and poorer retention [17], [18], [19].
Phase-change memory (PCM) is another promising nonvolatile memory technology [20], [21] that depends on the conversion of chalcogenide-based material between crystalline and amorphous forms through joule heating. PCMs also have multilevel conductance states. The crystalline state transition requires a high temperature for a long enough duration, resulting in a large delay and power consumption for writing the PCM. In addition, PCMs suffer from slow resistance drift [22].
Ferroelectric field-effect transistors (FeFETs) have a structure similar to that of conventional transistors but utilize a ferroelectric insulator layer as the dielectric layer. The application of a gate voltage induces polarization switching in the ferroelectric layer, modulating the conductance of the channel in FeFETs. By using HfOx thin films as the dielectric layer instead of perovskites [23], the fabrication of FeFETs becomes compatible with CMOS technology, resulting in a moderate memory window and good data retention. Similar to memristors, the polarization-induced conductance modulation in FeFETs is ideal for constructing synaptic plasticity [24], [25]. In addition, polarization in FeFETs exhibits an accumulation effect where the device state abruptly switches after a certain number of pulses is applied. By harnessing this device dynamics, FeFETs can be used to implement capacitorless integration neurons [26], [27].
An electrochemical random-access memory (ECRAM) device [28], [29] is a three-terminal memory device similar to an FeFET, but with an insulating electrolyte layer between the metal gate electrode and conductive channel. Under the electric field induced by the applied gate voltage, ionic transporting between the electrolyte and channel modulates the device conductance. The analog conductance tuning of ECRAMs is more stable than that of memristors due to deterministic ion motion. However, there are still some difficulties in the large-scale integration of ECRAMs and CMOSs at present, such as contamination caused by ions and the need to withstand high temperatures in the back end of the line.
A flash memory device is a conventional nonvolatile memory device that can store multibit weights by storing electrical charge in the floating gate. It is available in both NAND and NOR array structures and is an established technology. Compared to other emerging memories, flash has a larger memory window and has matured its 3D integration technology. Recently, vertical split-gate flash has been fabricated to enhance the performance of flash in advanced technology [30]. Combined with heterogeneous integration, flash-based CIM can provide a very high computing density [31].
In addition, other emerging memory devices have been widely studied for neuromorphic computing, including ferroelectric tunnel junctions [32], [33] and magnetoresistive random-access memory (MRAM) [34]. The device structures of representative memory devices are shown in Figure 2. The different behavior characteristics of these devices are applicable for various types of neuromorphic applications, as discussed in the following section.
Figure 2. Illustration of emerging memory devices. (a) Filament-type memristor. (b) Interfacial memristor. (c) PCM. (d) FeFET. (e) ECRAM. (f) Split-gate flash.
Currently, neuromorphic computing based on emerging devices can primarily be divided into two types. One type is CIM, which draws inspiration from the structure of BioNNs. The other type is brain-like computing, which simulates biological neural units and learning mechanisms. Emerging memory-based CIM can be broadly categorized into two types: inference-only CIM and CIM with in situ training. For CIM, memory devices function as tunable weights, requiring fine-tuning of analog conductance. The reliability requirements for these two types of applications differ [2], [35]. In inference-only CIM, the overhead of iterative read–verify can be disregarded as mapping software-trained weights to the memory array is performed only a few times. Therefore, the critical metrics center on the number of distinguishable conductance levels, device retention, conductance range, and reading noise as these factors significantly affect the weight mapping and sensing precision. Rao et al. developed a denoising programming method that reduces random reading noise [36]. An array of ${256}\times{256}$ Ti/Ta/HfO2/Al2O3/Pt memristors achieved up to 2,048 conductance levels with a ${<}{0}{.}{4}{-}$µA read current fluctuation under a 0.2-V read voltage. On the other hand, in situ training requires frequent weight updating, so endurance, write power consumption and latency, programming nonlinearity, and asymmetry significantly impact the in situ training’s performance.
For brain-like computing, to emulate behaviors of biological neural units, memory devices require dynamics and nonlinearity. To implement synaptic plasticity like spike-time-dependent plasticity (STDP) and paired-pulse facilitation, conductance relaxation and nonlinear I–V behavior can be utilized, in which the conductance changes nonlinearly with the applied pulse rate, intervals, and amplitudes [15], [37]. Several studies showed that device-based neurons can emulate multiple oscillating and firing modes [38], [39]. Moreover, temporal filtering of devices has been leveraged to implement artificial neural dendrites [40].
Emerging memory device-based CIM capable of parallelizing MVM operations can significantly accelerate the computing of ANNs. On the one hand, a considerable amount of computation is performed in parallel based on Kirchhoff’s law. On the other hand, the weights are directly mapped to the computing array to avoid frequent weight transfer. For example, in the crossbar array structure (Figure 3), a synapse cell storing the weight is located at the intersection of the bitline (BL) and sourceline (SL). Vertical SLs are clamped to a fixed clamp voltage ${V}_{\text{slc}},$ while input voltages are applied to horizontal BLs through digital-to-analog converters (DACs). The current converged at each SL is ${I}_{{\text{out}}{<}{i}{>}} = {\Sigma}_{{j} = {1}}^{N}{G}_{j,i}\times{(}{V}_{{\text{in}}{<}{j}{>}}{-}{V}_{\text{slc}}{)},$ in which ${V}_{{\text{in}}{<}{j}{>}}{-}{V}_{\text{slc}}$ represents the input ${A}_{{<}{j}{>}},$ and the MVM results are obtained by quantizing the converged SL current ${I}_{\text{out}}$ through analog-to-digital converters (ADCs). In this scenario, a single readout operation can process ${M}\times{N}$ multiplication-and-accumulations (MACs), including ${2}\times{M}\times{N}$ operands, where N refers to the number of input parallelisms and M corresponds to the number of readout parallelisms. To represent multibit input values, pulse amplitude or pulsewidth encoding can be used, as depicted in Figure 3(c). Weighted coding is a well-accepted technique for balancing both precision and efficiency. For instance, an 8-bit input is divided into two 4-bit sections with a weight ratio of 16:1. The sensed outcomes of each section are weighted and summed to generate the final MVM results. Similarly, multibit weights can also be fragmented into multiple columns, called bit-slicing [Figure 3(d)] [41]. Regarding bipolar inputs and weights, two methods include mapping positive and negative weights to two separate arrays, followed by differentiating the results to obtain the final output, or using a differential 2T2R structure [42] to combine the positive and negative parts into a single array.
Figure 3. (a) MVM operations in ANNs. (b) MVM based on RRAM array. (c) Amplitude coding, pulsewidth coding, and weighted coding. (d) Bit-slicing for weight. DAC: digital-to-analog converter; ADC: analog-to-digital converter; BL: bitline; SL: sourceline.
Emerging memory-based CIMs reported in the literature can be broadly categorized into two groups: full-precision CIM and limited-precision CIM, where “full-precision” and “limited-precision” refer to the accuracy of result quantization at the array level. In the following we will discuss features of these two CIM modes.
The full-precision CIM produces lossless quantization for every input batch, meaning that the input of 1 multiplying weight of 1 acts as the least significant bit (LSB) in the binary outcomes. This implies that if the input parallelism is M, and the number of weight levels and input levels are W and N, then the minimum quantization precision required is ${(}{\text{log}}{2}{(}{M}{)} + {\text{log}}{2}{(}{W}{)} + {\text{log}}{2}{(}{N}{)} + {1}{)}$ bits. To achieve this, it is essential to ensure a nonoverlapping distribution of each signal level to accurately sense each level without producing any errors. Thus, a high ON/OFF conductance ratio and small conductance variation are desired to generate a more distinguishable distribution for each readout level [43]. Both the input and weight are often binarized in full-precision CIMs to achieve a larger signal margin, and the input parallelism is kept low to obtain reduced logic ambiguity, ignorable current leakage, faster read latency (<10 ns), and a lower parasitic. In this parallelism setting, readout ADCs or sense amplifiers (SAs) utilize 5-bit precision or less to achieve the full-precision quantization [44]. Furthermore, the lossless quantization in full-precision CIMs allows for flexible digital operations, such as shift-and-add. Direct subtraction of the corresponding quantized codes for positive and negative weights can also result in bipolar MVM outputs.
On the other hand, for limited-precision MVM, the number of bits in the output readout is not determined by the quantity of input and weight levels or the system’s parallelism, but rather by the required accuracy levels of the algorithm. Specifically, if an N-bit quantization precision is required by the algorithm, the LSB of the output readout should be equal to the maximum output range divided by 2 to the power of N [45]. Here, the “maximum output range” refers to the signal range covered by all outcomes of the network. This mode is suitable for high-parallelism CIM, where multibit inputs and weights can boost computing power. However, it does result in narrowed quantization resolution due to the read voltage range and device conductance window not being proportionally enlarged. A full-precision readout would require an excessively high demand for quantization precision that would cause significant latency and power overhead. For instance, with 512 inputs, eight distinguishable weight levels, and 4-bit input, a one-time quantization precision of 17 bits would be required for a full-precision readout. In contrast, the limited-precision mode offers a better balance between efficiency and performance. It is important to note that, due to the precision loss during limited-precision CIM quantization, subtraction operations must be performed in the analog domain to prevent information loss, as depicted in Figure 4(a).
Figure 4. (a) Information loss in the subtraction of limited-precision quantization. (b) Definition of the signal range of limited-precision MVM.
It is important to bear in mind that the terms “full precision” and “limited precision” refer to the accuracy of readout quantization at the array level, not the precision of weight devices. While using analog devices as weights may appear to be more precise than binary cells, it is vital to consider that the overlapping conductance distribution and reduced signal margins in analog weight cells can make precise readout challenging.
These two modes of CIM are suitable for different application scenarios, and the choice of array size and computing precision should be carefully considered based on several factors, such as the number of algorithm parameters, accuracy requirements, energy consumption, and area limitations. Table 1 summarizes some characteristics of these two types of CIM from the present works. Here we briefly analyze the reasons for the different characteristics of the two models in terms of energy efficiency and computing power density.
Table 1. Characteristics of full-precision CIM and high-parallelism CIM.
From the perspective of input circuits, in full-precision but low-parallelism CIM, binary inputs can be applied to the wordlines (WLs) in the memory array, which connect to the gate of transistors. This structure lowers the requirement of driving capability and eliminates the IR drop. The application of inputs only necessitates switches and a global buffer. However, in limited-precision but full-parallelism CIM, multilevel inputs can only be utilized in crossbars, where the input voltage is applied to low-impedance nodes. To meet the demands of precise and swift voltage setup, power-hungry amplifiers with feedback become unavoidable.
Full-precision CIMs are usually designed with high energy-efficiency applications but with medium computing power and computing density, while limited-precision CIMs are more suitable for high computing power applications.
From the perspective of readout circuits, while a low-parallelism CIM with full precision requires multiple inputs for computing multibit inputs, it benefits from a smaller array size and parasitic effects, enabling a faster voltage settling. Additionally, the relaxed resolution requirements, such as the low-resistance state cell current typically ranging from 4 to 20 ${\mu}$A for CIM chips [43], [45], [46], make it possible to achieve multibit quantization at once, ultimately reducing readout latency. On the other hand, the effective differential signal distribution present in full-parallelism but limited-precision CIM is lesser than the single-end signal amplitude [42], as depicted in Figure 4(b). Moreover, employing multibit inputs and weights leads to a reduction in the signal margin, thereby augmenting the need for higher quantization resolution. For ADCs limited by thermal noise, achieving an additional bit of precision translates to a fourfold increase in power consumption [47]. Thus, to mitigate the noise, ADCs intended for readout quantization usually demand a significant amount of power, leading to a decline in overall energy efficiency.
Regarding computing power density, full parallelism enables the completion of multiple operations simultaneously, while analog weights improve the weight density. Full-parallelism CIMs with large-size arrays result in lower overheads on peripheral circuits, thereby facilitating high computing density for the same number of parameters [48], [49]. Additionally, a larger array can accommodate a greater number of weights simultaneously, reducing the frequency of weight transfers.
Therefore, full-precision CIMs are usually designed with high energy-efficiency applications but with medium computing power and computing density, while limited-precision CIMs are more suitable for high computing power applications. From the perspective of brain computing, it is notable that the computing in brains is not accurately and accompanied by noise [50], [51]. Hence, the limited-precision but high-parallelism CIM seems more akin to how the human brain computes. To better exploit the advantages of emerging memory-based highly parallel computing, the learning mechanisms of the human brain remain to be further revealed.
As the basic operation in CIMs, MVMs can be implemented in multiple signal domains, including current, voltage, charge, and time, etc. In current-mode MVM, the cell current is controlled by the device conductance, shown in Figure 5(a). The current-mode MVM operation has the drawback of high quiescent currents, resulting in a large static power overhead [52]. Additionally, sensing currents induced by reading voltages implies that the precision of current-mode CIM is sensitive to the variation of clamp voltages caused by noise, offsets, and IR drop [46], [53], [54]. Nonetheless, current-mode CIM is expected to perform better with higher parallelism compared to other CIM modes due to the clamping circuit. For energy-efficient CIM applications, some studies have explored voltage-domain CIM, such as using the BL discharge rate [52] and the settled floating SL voltage [55] to represent the MVM calculation results. Figure 5(b) illustrates the proposed structure for such applications.
Figure 5. Illustrations for MVM in different signal domains. (a) Current domain. (b) Voltage domain. (c) Charge domain. (d) Time domain. TDC: time-to-digital convert.
Moreover, charge and time-domain MVMs are also employed in CIM hardware designs. In charge-mode CIM, the products of input and weight bits are responsible for controlling the bottom plate voltages of capacitors, further establishing the voltage of the common top plate [56], [57]. Finally, the top plate voltage is sampled and converted to the MVM result. The array structure is depicted in Figure 5(c). However, it is worth noting that larger capacitor areas can lead to decreased computing density. Time-domain MVM [58] also presents an efficient solution for high energy-efficiency CIM. This is due to sparse pulse activities and the absence of static currents, which contribute to enhanced energy efficiency. In this method of MVM, the delay of each cell is determined by the corresponding inputs and weights, as seen in Figure 5(d). The MVM results are later read out by time-to-digital converts (TDCs) in accordance with the delayed pulses.
Compared to voltage- and current-mode CIMs, charge and timing-mode CIMs are better suited for advanced technology due to the sensitivity of analog circuits to power and voltage scaling. The dynamic signal range in the voltage and charge domain is frequently restricted by the precharged voltage, thus limiting the signal margins. However, the voltage range in the voltage-mode domain is further limited by the read disturb. Table 2 summarizes the features of MVMs in different signal domains. Combining processing methods from different signal domains can leverage the strengths of each domain. For example, current-mode CIM-based SNNs transfer spikes in the time domain, enabling weight-and-sum processing with short latency and sparse information routing with low power consumption.
Table 2. Summary of features of different signal domain-based CIMs.
Emerging device-based CIM systems’ performance may suffer from nonideal properties of devices, circuits, and systems, making them less accurate than software-based simulations. Nonideal behaviors of devices primarily affect the precision of weight programming and readout. To address the impact of stochastic conductance fluctuations on weight mapping precision, read–verify methods are widely employed to constrain conductance states in narrow distributions [60]. However, multibit programming can lead to significant power and time overhead due to the iterative read–verify process. So, precision is often limited to four bits or less when programming single devices, resulting in a disparity between software-trained floating-point weights and finite device levels. Additionally, accuracy may suffer from conductance variation, drift, read noise, and other nonideal RRAM device characteristics. Some works propose incorporating RRAM behavior models and noise injection techniques into network training processes to enhance resilience to nonideal properties [61]. Hybrid training [45] is an effective strategy that enables the network to adapt to device behaviors by training part of the layers of the network in situ.
At the circuit level, large-scale arrays with circuit noise, capacitive parasitics, IR drop, and current leakage can degrade read speed and precision, particularly in current-mode CIM crossbar architectures. Fluctuations in the voltage of SL clamping have the potential to affect both static errors, such as readout circuit offsets and array current–voltage IR drop, and dynamic errors, such as noise and incomplete voltage settling. Input-aware clamp circuitry or the use of differential 2T2R weight and 2T1R weight structures can address these issues [42], [46], [62].
When it comes to processing large neural network computations, multicore systems are essential. However, their peak performance is inhibited by factors such as weight mapping, data input loading, and data routing among arrays, leading to latency. Furthermore, unbalanced task distribution can congest data routes among multiple cores. Fortunately, simulators can be utilized to scrutinize system performance and optimize weight mapping and array size under diverse structures [49], [63], [64].
In this section, we will review the CIM chips and systems based on emerging devices, ranging from array-level demonstrations to macrolevel chips and systems. Figure 6 is a road map of emerging device-based CIM hardware.
Figure 6. Road map of emerging device-based CIM hardware. MNIST: Modified National Institute of Standards and Technology; LSTM: long short-term memory. (Source: Adapted from [42], [45], [55], [65], [67], [69], [70], and [72].)
One early demonstration was in situ training on ${3}\times{3}$ binary image classification based on a ${12}\times{12}$ passive memristor crossbar [65], showcasing the potential for neural network acceleration. Afterward, various algorithm demonstrations were implemented using small-scale memristor arrays [66]. To overcome cell leakage and improve programming precision in large-scale arrays, 1T1R memristor arrays were used in several studies to implement algorithms such as image compression, convolutional filtering, and the in situ training of two-layer perceptions and long short-term memory (LSTM) networks [60], [67], [68].
Beyond array demonstrations, several prototype full-precision CIM chips based on emerging memory have been reported. In 2017, Su et al. [69] presented a nonvolatile RRAM-based CIM processor fabricated in 150-nm CMOS technology, consisting of four ${32}\times{32}$ RRAM MVM engines. In 2018, Chen et al. [70] implemented a 65-nm 1-Mb RRAM-based CIM macro for accelerating a binary neural network, achieving a 14.8-ns access time for a ${3}\times{3}$ convolutional kernel and adopting full-precision CIM mode. To mitigate the signal margin deterioration caused by increasing parallelism, Xue et al. [43] proposed a triple-margin small-offset current-mode SA that enlarges the sense margin by sampling and canceling the threshold mismatch of diode-connected load transistors, resulting in a threefold increase in the effective signal margin. The fabricated 1-Mb RRAM CIM core in the 55-nm process achieved an energy efficiency of 53.17 TOPS/W in 1 b-input, 3 b-weight, and 4 b-output mode. Hung et al. [52] proposed a dc-current-free CIM macro that achieved up to 1,286.4 TOPS/W in 1 b-input, 1 b-weight, and 3 b-output mode. In this scheme, the BL is first precharged to a fixed voltage and then discharges at different discharge rates depending on the input-activated WL and stored weights. Instead of using single-level cells (SLCs) as weight cells, Khwa et al. [71] used multilevel cells (MLCs) to improve the weight density and proposed a voltage-swing remapping voltage SA to enlarge the signal margin and rescale the sensed voltage range. In 2022, Huo et al. [72] reported the first 3D vertical RRAM based full-precision CIM macro, in which each memory cell supports the 2-bit weight. The 3D vertical RRAM density is 16.6 times higher than that of the previous 2D RRAM-based CIM.
Regarding high-parallelism CIM, Liu et al. [42] reported the first analog RRAM-based CIM chip for high parallelism, fabricated in the 130-nm technology. The chip adopted a differential 2T2R weight structure to largely cancel SL currents and alleviate the IR drop. This chip achieved high parallelism with an array size of 156.8 Kb and a read latency of 77 ${\mu}$s/image as well as a peak energy efficiency of 78.4 TOPS/W. Correll et al. [73] fabricated an SoC prototype chip integrating four isolated RRAM CIM tiles, each supporting the parallelism of 256 inputs and 32 readouts, with a 16-level RRAM weight cell. They proposed using a binary-weighted multicycle sampling ADC to weight the partial bitwise output and quantize the overall result, so only one-time quantization is needed for each MAC operation. The performance of recently representative CIM macro chips is summarized in Table 3.
Table 3. Summary of recently reported CIM macro chips. (Adapted from [44], [46], [52], [71], [73], and [74].)
To improve the performance of CIM systems, optimizations can be implemented at both the circuit and system levels. In 2022, a multiarray system integrating eight 2-Kb RRAM arrays was reported [45]. The system performed a five-layer convolutional neural network (CNN) and achieved an accuracy of more than 96%. It also demonstrated better energy efficiency and performance density than state-of-the-art GPUs. To address the precision loss caused by weight mapping, this work adopted a hybrid training method that performed in situ retraining of the last layer. Furthermore, convolutional kernels were replicated to RRAM arrays to parallelize the convolution process of serial sliding windows. Another voltage-mode CIM chip, named the NeuRRAM, was reported [55]. The chip included 48 RRAM-CIM bidirectional transposable neurosynaptic arrays and supported flexible calculation without duplicating ADCs and input buffers. Several hardware-algorithm co-optimization methods, such as model-driven chip calibration and noise-resilient neural-network training, were proposed to mitigate hardware nonidealities. The NeuRRAM demonstrated outstanding performance on various tasks, like achieving an error rate of 0.98% on the Modified National Institute of Standards and Technology (MNIST) dataset using a seven-layer CNN and 14.34% on the CIFAR-10 dataset using ResNet-20.
As mentioned previously, the device conductance is dependent upon the motion of conductive ions, exhibiting a wide range of dynamic and stochastic characteristics. It is therefore expected that such features could be harnessed in the design of brain-like computing systems, with the potential to realize higher energy efficiency and integration density compared to conventional CMOS-based systems. In the following sections, several behavioral attributes of the emerging memory and related demonstrations of brain-like systems will be discussed.
The selector device employed in passive crossbars to suppress leakage can result in abrupt conductance switching under varying voltage, as depicted in Figure 7(a). This threshold-switching behavior is widely utilized to mimic the firing behaviors of biological neurons and consequently facilitate the construction of SNNs. Mott device-based neurons have been demonstrated to emulate multiple firing modes of biological neurons [38], [39]. Ag filament-based diffusive memristors and FeFETs are also adopted to implement the leakage integrate-and-fire (LIF) neurons, which are commonly used in SNNs [26], [75], [76]. Device dynamics are leveraged for implementing synaptic plasticity. Kim et al. [37] utilized the second-order behavior of memristors to implement STDP, whose conductance change depends on the interval time between applied pulses at both terminals. Li et al. [40] introduced a dendrite device exhibiting a nonlinear response in its conductance with respect to the amplitude and interval time of the continuously applied pulses. The properties of this device resemble the nonlinear filtering behavior of biological dendrites, and it could be employed in the creation of neural network systems that incorporate dendritic structures, unlike the point-neuron models used in conventional ANNs. Some emerging devices possess intrinsic stochasticity, which has been leveraged in physically unclonable functions [77], true random number generators [78], Bayesian neural networks [79] as well as simulated annealing algorithms [80] and others. A schematic of device behaviors and the related applications are shown in Figure 7.
Figure 7. (a) Device behavior schematic of threshold switching, nonlinear dynamics, and stochastic. (b) Synapse device behaves like STDP. (c) Diffusive memristor as an LIF neuron. (d) Dendrite device. LIF: leakage integrate and fire. (Source: Adapted from [37], [75], and [81].)
Neuromorphic computing demonstrations have been achieved using emerging memory devices. For example, Wang et al. utilized ${8}\times{8}$ drift memristor-based synapses and eight diffusive memristor-based neurons for unsupervised learning. The synapses evolved to fixed patterns after training using simple STDP and lateral inhibition under the stimuli of input images [82]. Fu et al. [83] developed a forming-less V/VOx/HfWOx/Pt device with threshold-switching and nonvolatile resistive-switching behavior, enabling capacitor-free neurons and high-precision synapses in a single device, thus avoiding process incompatibilities. A fully memristive SNN based on the fabricated device achieved ∼10 fJ/per operation for one synapse with an accuracy of 86% on the MNIST dataset using in situ learning based on the remote supervised method (ReSuMe). Furthermore, an SNN system was demonstrated in [84] integrating hybrid memristor–CMOS stochastic LIF neurons and resistive-switching memristor synapses. The neuron emulated the “all-or-none” feature and supported a simple Hebbian learning rule along with lateral inhibition to achieve the winner-take-all feature. A two-layer SNN was also demonstrated, in which the first layer underwent unsupervised training in situ, and the second layer was supervised trained to output classified results.
The previous study considered the neuron as a conventional point model and overlooked the interaction among the neuron components. In contrast, [81] constructed neuromorphic systems with a complete neuron structure, comprising somas, dendrites, and synapses using various memristors. The serial connection of dendrite and Mott soma devices in the neuron enables nonlinear filtering behavior, which enhances robustness to input noise and enriches temporal information processing capabilities. A full-memristor LSTM network was implemented, incorporating 75 memristor synapses, 18 dendrites, and three somas, achieving 96% accuracy on the Nanyang Technological University-Red Green Blue (NTU-RGB) dataset. By leveraging the filtering behavior of dendrite devices, the power consumption of the system was significantly reduced, being 2,000 times lower than that of a GPU. Besides device-level simulation, some systems adopt a brain-like architecture.
RC is a novel computing paradigm that efficiently captures spatiotemporal signals. The training of RC is highly efficient, requiring only modulation of the linear readout layer. To create a reservoir layer without recurrent connections, dynamic memristors have been leveraged to exhibit nonlinear and temporal filtering features, providing rich temporal information to the reservoir. Zhong et al. [85] reported a fully integrated RC system using dynamic memristors that included a 24-dynamic-memristor-based reservoir layer and a readout layer composed of ${192}\times{8}$ drift memristors. The voltage buffer connects the node states of the reservoir directly to the readout layer, eliminating the need for ADCs. The system achieved 96.6% accuracy for detecting temporal arrhythmia and 97.9% accuracy for recognizing spatiotemporal dynamic gestures.
Table 4 is a summary of representative demonstrations of emerging memory device-based brain-like computing.
Table 4. Summary of emerging device-based brain-like demonstrations.
The utilization of emerging memories that possess high integration densities, nonvolatility, and dynamic behaviors provides a promising approach to construct large-scale neuromorphic computing systems capable of achieving advanced performance with high energy efficiency. Here we put forward some perspectives about improving the neuromorphic computing systems from the device to the system level.
At the device level, optimizing the device analog behavior is essential. Keeping the device conductance within an appropriate range is also crucial for balancing current consumption and readout accuracy. Emerging memory-based CIMs in the charge and time domains require further investigation at the circuit and algorithm level due to their suitability for advanced CMOS technology. To maximize full-precision CIM’s parallelism, two key factors need addressing by optimized circuit designs: establishing a larger signal margin by widening the gap between 0 and 1 states of weight cells and developing compensations for the array IR drop.
At the system level, it is necessary to combine CIM with a CPU to build a general-purpose processor to support implementing all operations on chip [87]. To achieve high efficiency, it is necessary to minimize the data transfer frequency and reduce the speed gap between CIM and CPU processing while maximizing CIM core utilization. This requires optimization of the system architecture, instructions, and data routing. Another crucial point to explore at the system level is process integration, which focuses on 3D integration and optimizing selector devices to increase the integration density and construct 3D monolithic integration systems. It also involves integrating multiple modules, such as sensing, storage, and computing, into a single chip, further reducing data transmission and enhancing the energy efficiency and data security of edge computing. Some monolithic 3D integration implementations have been reported. For example, [88] monolithically integrated silicon-based CMOS logic, RRAM-based CIM, and carbon nanotube FET-based ternary content-addressable memory layers. They demonstrated a one-shot learning task with 97.8% accuracy on the Omniglot dataset, with 162× lower energy efficiency than the GPU. From a system perspective, the multimodal system is expected to integrate advantages of multiple types of neuromorphic computing. For example, ANNs and SNNs have their own advantages in task processing [5], with ANNs focusing on accuracy and SNNs having an advantage in processing binary bitstreams containing time information, such as Deep Visibility Series data. Some works have integrated CIM-based ANNs and SNNs [89] to combine high energy efficiency and accuracy. In addition, a multimodal system that integrates multiple sensor arrays, CIM-based preprocessing units, and nonvolatile memory is expected to facilitate high-performance edge computing.
Moreover, a strict methodology for benchmarking CIMs is currently inadequate [90]. Presently, the accuracy of CIM hardware is reported based on the accuracy of specific network algorithms, but such an evaluation criterion is uncertain and can be easily manipulated. Furthermore, evaluating the signal-to-noise ratio is challenging due to its dependency on array loads and weight and input patterns. Additionally, published works can only report the performance under specific precisions, such as integer 4 and integer 8. However, different circuit structures and computing principles have unique calculation processes, making it difficult to extrapolate performances under different precision levels. For example, energy efficiency at 1-bit precision cannot be easily determined by multiplying the efficiency under 4-bit by 4. In conclusion, the high level of customization involved in analog CIM hinders the establishment of uniform benchmarks.
In this review, we have provided a comprehensive summary of the application of RRAM-based CIM for neural network acceleration as well as demonstrations of emerging memory for other brain-like computing purposes. Different array structures and MVM modes are suitable for CIM chips with different performance requirements. In addition, emerging memories exhibiting diverse properties are also well suited for the realization of diverse types of neuromorphic computing. To achieve a reliable and high-performance neuromorphic computing system, collaborative optimization is required at every level from the bottom-up device manufacturing to high-level system algorithms.
This work was supported in part by the STI 2030-Major Projects (2021ZD0201200), the National Natural Science Foundation of China (92064001 and 62025111), the XPLORER Prize, the Shanghai Municipal Science and Technology Major Project, and the Beijing Advanced Innovation Center for Integrated Circuits.
Qiumeng Wei (wqm20@mails.tsinghua.edu.cn) is with The School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China.
Bin Gao (gaob1@tsinghua.edu.cn) is with The School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China.
Jianshi Tang (jtang@tsinghua.edu.cn) is with The School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China.
He Qian (qianh@tsinghua.edu.cn) is with The School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China.
Huaqiang Wu (wuhq@tsinghua.edu.cn) is with The School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China.
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Digital Object Identifier 10.1109/MED.2023.3296084
Date of current version: 15 September 2023