Silicon Earth: A Historical Perspective on the Invention/Discovery of the Transistor

©SHUTTERSTOCK.COM/GOLAM-ROBBANY

History is the essence of innumerable biographies.

—Thomas Carlyle

This article traces the history to the invention/discovery of the transistor. Seventy-six years of the transistor. My, my, time flies. Such a remarkable little piece of quantum physics in action. The transistor was invented/discovered on 16 December 1947, then introduced to the world on 23 December 1947 [2], an Earth-changing moment. It was roughly the size of your thumbnail. In 2023, transistors are virtual sized and speed-of-light fast, and, importantly, they cleverly possess, just like the original, that unique golden attribute of amplification, making tiny voltages and currents larger. There are over 10²⁴ transistors on Earth in 2023, made possible by the jaw-dropping exponential growth patterns embodied in Moore’s law. It is instructive to compare the first transistor with a contemporary embodiment (Figures 1 and 2).

Figure 1. A scaled replica of the world’s first point contact transistor, using authentic materials. This one was made by Milad Frounchi, in 2021. Frounchi is one of the author’s former Ph.D. students, and he has a love of crafting intricate miniatures.

Figure 2. A scanning electron microscope cross section of a modern SiGe bipolar CMOS technology, showing an SiGe HBT, CMOS transistors, and the metalization superstructure. (Source: P. Chevalier, STMicroelectronics; used with permission.)

Transistors are ubiquitous to modern life, whether seen or unseen by both purveyors and consumers of technology. Surely the word transistor should be added to the vocabulary of every single person on Earth. The simple fact is that all modern technology, without exception, from smartphones to automobiles to planes to the Internet to GPS, would instantly cease to function if the transistor were subtracted from the planet. Want to decode the human genome, use CRISPR to cure a disease, or build a better crop, develop a messenger ribonucleic acid vaccine for a pandemic, hone artificial intelligence and virtual reality without a transistor? Never gonna happen! In fact, in terms of its impact on the trajectory of civilization writ large, one could fairly argue that the invention of the transistor is the most important invention/discovery in human history. Bold words but quite defensible [1].

What History Can Teach Us

To my mind, there are four compelling reasons to examine the historical foundations of any given technological field:

Know the roots of your chosen profession: This is true whether you are a concert pianist, a professional baseball player, a computer programmer, a materials scientist, an architect, a chef, or an IC engineer. The better you know the roots of your field, the better able you will be to place yourself in its context and find the best path forward. If you don’t aspire to accomplish something meaningful (and hopefully new) with your career … you chose the wrong profession. Besides, for something as influential as micro/nanoelectronics in the evolution of civilization, I would argue that this particular history should be known by all folks, not just technologists: brothers and sisters, moms and dads, grandmas and grandpas. I strongly suspect that 1,000 years hence, the 76 years of intense technological innovation surrounding this field, from roughly 1947 to 2023, will burn very brightly in the historical record.
Learn how your predecessors innovated: It is always instructive for the next generation to glimpse how the pioneers of their chosen profession accomplished all that they did. Seeing how others innovate will make innovation easier for you. Some takeaways from this particular history: 1) serendipity often plays a major role in discovery (careful with serendipity: not just luck but, rather, being in the right place at the right time with the training needed to fully appreciate and then run with what you just happened upon). This is an important lesson for all budding innovators to glean early on and should give all us mere mortals extra incentive. 2) Multidisciplinary training matters a lot. 3) Proper handling of your inventions is key to defining their future. 4) Business acumen and selling savvy can be awfully important to success in technological fields.
History is defined by people, not events: This is the point of Thomas Carlyle’s quotation at the beginning of the article, and it runs counter to many people’s naive notion of what history is. There are clearly exceptions to this history-shaping rule of people define events (not vice versa), but they are rare. You and I can change history. We can revector the many evolutionary threads that span human history. This is truly an empowering idea. To my mind, history is best approached not as a dry collection of facts and dates but, rather, as a fascinating mélange of unusual personalities and motivations.
History can be fun: OK, believe it or not, the history of technology can make for some pretty darn interesting reading. This may surprise the masses, but, yep, it’s true—history can indeed be fun. Given the wacky personalities of the best and brightest minds walking the planet on any given day of the week, this really shouldn’t surprise you. The history of micro/nanoelectronics is indeed often soap opera-ish and chock-full of eccentric personalities, massive egos, and backstabbing. Fact is often stranger than fiction!

The Uniqueness of Microelectronics

From a broad-brushed historical perspective, many aspects of the development of microelectronics technology are strikingly unusual. For instance, most technologies have traditionally proceeded from “art” to “science,” rather than the other way around. In the steel industry, for instance, literally centuries of empirical craftsmanship (the “art”) transpired before even the most rudimentary scientific underpinnings were established (the “science”). People knew how to produce high-quality steel and fashion it into all sorts of sophisticated objects, from tools to cannons, long before they understood why steel worked so well. This knowledge base was largely empirically driven—as they say, practice makes perfect. Part of this inherent difficulty in applying science to steel production lies in the exceeding complexity of the materials involved. Steel is simply a very complicated material, chock-full of nuances and unknown variables (this is no longer true, obviously). Microelectronics, by contrast, represents one of the rare instances in the history of technology in which “science preceded the art” [3].

Part of this difference between microelectronics and all other technologies lies in the fundamental problems associated with the materials involved. For microelectronics, we are dealing with a near-perfect single crystal of regularly arranged atoms of a single element—silicon (Si)—about as simple and ideal a material as one can imagine to apply the scientific method to. By most accounts, and for obvious reasons, today, Si is far and away the best understood material on Earth. In such “simple” problems, trivial (literally, back-of-the-envelope) theory can often work astoundingly well in capturing reality. For instance, imagine introducing a tiny number of phosphorus atoms into Si (e.g., add one phosphorus atom for every 100 million Si atoms). Question: How much energy does it take to release the extra electron bound to the incorporated phosphorus atom into the crystal (this is called the dopant ionization energy and is very important information for building transistors and circuits)? Hint: A scratch of the head and a puzzled look would be appropriate here for most readers. Answer: This problem can be well described by a simple “toy model” of a hydrogen atom (the Bohr model, 1913), something every first-year college science and engineering student learns, and in 2 s (OK, three) of simple calculations, we have an answer accurate to within a factor of three. Correct answer? It’s 45 meV. Toy model answer? We have 113 meV. This accuracy is rather amazing if you stop and think about it, given the complex quantum mechanical nature of the actual problem involved. Science works quite well in such idealized venues, and, in the end, this turns out to be pivotal to the ultimate success of microelectronics technology because, as a circuit design engineer, for instance, I do not have to stop and worry about performing a detailed first-principles solution to Schrödinger’s equation, the pesky (read: exceedingly difficult to solve) workhorse of quantum mechanics, to know how to bias my transistor in the electronic circuit I am constructing. If I did, there clearly wouldn’t be many smartphones and computers around.

It is interesting that microelectronics technology, in fact, has followed the popular (but, alas, commonly misperceived) direction of technological innovation—first discover the science, and when the science is mature, then hand it off to the engineers so that they can refine and develop it into a viable technology for society’s happy use. A glance at the historical record indicates that this common view of how technological innovation should ideally proceed, however appealing, is rarely borne out in practice. Microelectronics is one of the very few exceptions [4]. The transistor was born from a rich legacy of science but virtually nonexistent art. By art, in this context, I mean the accretion of skills, techniques, and engineering approaches that would permit the fabrication of microscopic structures called for by the transistor inventors for feasibility demonstrations and design engineers for subsequent refinements. Just who exactly were the purveyors of the requisite art of this fledgling microelectronics empire? Interestingly, and unique at least to the time, these individuals were trained scientists (physicists, primarily) but working principally as engineers, all the while searching for (profitable) inventions. They were a new breed, a fascinating amalgam of scientist–engineer–inventor.

What exactly drove the world inexorably to the transistor and why? For brevity, I omit the fascinating trajectory of events and discoveries that led us to the transistor and save it for another day [1].

The Invention/Discovery of the Transistor

After World War II, the famous “Transistor Three” assembled at Bell Telephone Laboratories (“Bell Labs”), in Murray Hill, NJ, USA (Figure 3), and began their furious search for a solid-state amplifying device, a semiconductor triode (our soon-to-be transistor) [5], [6], [7]. Hired by Director of Research Mervin J. Kelly (later, president of Bell Labs), in 1936, William Shockley, a theoretical physicist, in 1945 became group leader of a new “semiconductor” group containing Walter Brattain, an experimental physicist extraordinaire (who joined Bell Labs in 1929), and John Bardeen, a theoretical physicist (who joined Bell Labs in 1945). Kelly’s dream, put to Shockley as a provocative challenge of sorts for his new team, was “to take the relays out of telephone exchanges and make the connections electronically.” Kelly was after a replacement of the notoriously unreliable mechanical telephone relay switch but could have equivalently asked for a replacement of the equally unreliable vacuum tube amplifier of radio fame, the electrical equivalence of a solid-state amplifier and electronic switch being implicit. Importantly (and, sadly, quite unusual by today’s standards) Kelly assembled this “dream team” of creative talent and then promptly gave it carte blanche over resources and creative freedom, effectively saying “I don’t care how you do it or how much money you spend, but find me an answer, and find it fast.”

Figure 3. The Bell Labs facility.

During the spring of 1945, Bell Labs issued an important authorization for work explicitly targeting fundamental investigations into a half dozen classes of new materials for potential electronics applications, one of which, fortuitously, was semiconductors [principally, Si and germanium (Ge)]. The Transistor Three all had some experience with semiconductors and, thus, logically focused their initial efforts on amplification using semiconductors, based on Shockley’s pet concept of a capacitor-like metal–semiconductor structure not unlike that of a modern MOSFET. This search direction culminated in more than a few of what Shockley termed “creative failures.” The reason such devices failed was soon understood (by Bardeen) to be related to surface defects in the semiconductor crystal itself.

Armed with Bardeen’s theory, Bardeen and Brattain began to look for ways to effectively “passivate” (remove the defects from) the surface of the Si crystal, into which Brattain had stuck two metal cat’s whiskers for electrodes. Unfortunately, condensation kept forming on the electrodes, effectively shorting them out. In a creative leap, on 17 November 1947, Brattain dumped his whole experiment into nonconducting (distilled) water (he knew a vacuum would have worked better but later said that it would have taken too long to build). To his amazement, he thought he observed amplification. When Bardeen was told what had happened, he thought a bit and then, on 21 November, suggested pushing a metal point into the semiconductor surrounded by a drop of distilled water. The tough part was that the metal contact couldn’t touch the water; it could touch only the semiconductor. Ever the clever experimentalist, Brattain later recalled, in 1964 [5], “I think I suggested, ‘Why, John, we’ll wax the point.’ One of the problems was how do we do this, so we’d just coat the point with paraffin all over, and then we’d push it down on the crystal. The metal will penetrate the paraffin and make contact with the semiconductor, but still we’d have it perfectly insulated from the liquid, and we’ll put a drop of tap water around it. That day, we in principle, created an amplifier.”

Once they’d gotten slight amplification with that tiny drop of water, Bardeen and Brattain figured they were onto something significant. They experimented with many different electrolytes in place of the water and consistently achieved varying degrees of amplification. On 8 December, Bardeen suggested that they replace the Si with (in retrospect) less defective Ge. They suddenly achieved an amplification of 330× but, unfortunately, only at very low frequencies (rendering it unsuitable for the envisioned applications). Bardeen and Brattain thought the liquid might be the problem, and they replaced it with Ge dioxide. On 12 December, Brattain began to insert the point contacts. To his chagrin, nothing happened. In fact, the device worked as if there were no oxide layer at all. As Brattain poked the gold contact repeatedly, he realized that no oxide layer was present; he had washed it off by accident. Furious with himself, he serendipitously decided to go ahead and play a little with the point contacts anyway. To his intense surprise, he again achieved a small amplification but, importantly, across all frequencies. Eureka! The gold contact was effectively puncturing the Ge and passivating the crystal surface, much as the water had.

During that month, Bardeen and Brattain had managed to achieve a large amplification at low frequencies and a small amplification for all frequencies, and now they cleverly combined the two. They realized that the key components to success were using a slab of Ge and two gold point contacts located just fractions of a millimeter apart. Now suitably armed, on Tuesday afternoon, 16 December 1947, Brattain put a ribbon of gold foil around a plastic triangle and cut it to make the point contacts. By placing the vertex of the triangle gently down on the Ge block to engage the point contacts, he and Bardeen saw a fantastic effect: a small signal came in through one gold contact (the electron “emitter”) and was dramatically amplified as it raced through the Ge crystal (physically the “base” of the contraption) and out the other gold contact (the electron “collector”). Success!

The first point contact semiconductor amplifier had been invented, or discovered, depending on your point of view (Figure 4). I think of it as an invention/discovery. Bardeen and Brattain’s seminal paper on their transistor (remarkably, only one and one-half pages long; refer to Figure 5) was published in Physical Review, on 15 July 1948 [2]. Hint: there was no IEEE Electron Device Letters.

Figure 4. (a) The famous point contact transistor, the first solid-state amplifying device, invented by Bardeen and Brattain. Bardeen and Brattain discovered that by placing two gold contacts close together on the surface of a crystal of Ge through which an electric current was flowing, a device that acted as an electrical amplifier was produced. (Source: Alcatel-Lucent; used with permission.) (b) A schematic of the device. See also the companion article in this issue by Kaufman and Dallesasse.

Figure 5. The paper published by Bardeen and Brattain debuting their invention of the point contact transistor to the world. They acknowledge Shockley’s contribution in the last paragraph.

The name transistor was coined by J.R. Pierce, following an office ballot (read: a betting pool). Important: all cool widgets must have cool widget names. He started with a literal description of what the device actually did electrically, a “transresistance amplifier,” which he first shortened to “transresistor” and then, finally, to “transistor” [5]. Finito, it stuck.

After an additional week of experimental refinement, the formal transistor demonstration was repeated for Shockley’s semiconductor group (Gibney, Shockley, Moore, Bardeen, and Pearson, with Brattain at the wheel) and, importantly, two of the Bell Labs’ “brass” (a research director, R. Bown, and Shockley’s boss, H. Fletcher—ironically, Kelly, who launched it all, was not informed for several more weeks), on Tuesday afternoon, 23 December 1947, just before everyone left for the Christmas holidays (it was already snowing), which is now regarded as the official date stamp for the invention of the transistor and the birth of the Information Age. A pivotal moment in human history, and worth remembering. I certainly demand that of my students.

In a telling comment, Shockley later said, “My elation with the group’s success was balanced by the frustration of not being one of its inventors” [4], [8]. It is ironic, then, that the most famous picture of the event contains all three men, with Shockley front and center, hovering over the transistor as if it were his own baby (Figure 6). On the famous portrait of the Transistor Three, Nick Holonyak, in an interview with Frederick Nebeker, on 22 June 1993, said, “[John Bardeen] said to me, ‘Boy, Walter really hates this picture.’ I said to him at the time, ‘Why? Isn’t it flattering?’ That’s when he made this face at me, and shook his head … He said to me, ‘No. That’s Walter’s apparatus, that’s our experiment, and there’s Bill sitting there, and Bill didn’t have anything to do with it.’”

Figure 6. The famous Transistor Three: William Shockley (seated), Walter Brattain (right), and John Bardeen (left). (Source: Alcatel-Lucent; used with permission.)

Meanwhile, Shockley spent New Year’s Eve alone in a hotel in Chicago, IL, USA, where he was attending the American Physical Society Meeting. He spent that night and the next two days essentially locked in his room, working feverishly on his idea for a new transistor type that would improve on Bardeen’s and Brattain’s point contact device. Why? Primarily because he felt slighted. It has been pointed out that perhaps the most important consequence of the invention of the point contact transistor was its direct influence on Shockley as an incentive to discovery. “This experience and the resulting emotion wound Shockley’s spring so tightly that in the following 10 years, he was the author of the most remarkable outpouring of inventions, insights, analyses, and publications that [any] technology has ever seen. It is only a slight exaggeration to say that he was responsible for half of the worthwhile ideas in [all of] solid-state electronics” [3].

Shockley believed he should have received credit for the invention of the transistor, given that his original idea of manipulating the surface of the crystal set the stage for Bardeen and Brattain’s eventual success … and, of course, because he was the boss. Not surprisingly, the Bell Labs lawyers (and management) didn’t agree. And so, over the New Year’s holiday, Shockley fumed, scratching page after page into his lab notebook, primarily focusing on his new idea for constructing a transistor from a “sandwich” of different semiconductor layers all stuck together. After some 30 pages of scribbling (refer to Figure 7), the concept hadn’t quite gelled, and so Shockley set it aside.

Figure 7. Page 128 of Shockley’s technical journal, showing his idea of the BJT. (Source: Alcatel-Lucent; used with permission.)

As the rest of the semiconductor group worked feverishly on improving Brattain and Bardeen’s point contact transistor, Shockley remained aloof, concentrating on his own ideas, secretive to the extreme. On 23 January, unable to sleep, Shockley sat at his kitchen table early in the morning, when the lightbulb suddenly switched on. Building on the semiconductor “sandwich” idea he’d come up with on New Year’s Eve, he became quickly convinced that he had a solid concept for an improved transistor. It would be a three-layered device. The outermost pieces would be semiconductors with too many electrons (n-type), and the piece in the middle would have too few electrons (P-type). The middle semiconductor layer would act like a faucet: as the voltage on that part was adjusted up and down, he believed it could turn current in the device on and off at will, acting as both a switch and an amplifier.

Predictably, Shockley didn’t breathe a word. The basic physics behind this semiconductor amplifier was very different from Bardeen and Brattain’s device because it involved current flowing directly through the volume of the semiconductors, not along the surface, and Shockley proceeded to derive its operational theory. On 18 February, Shockley learned that his idea should, in fact, work. Two members of the group, Joseph Becker and John Shive, were conducting a separate experiment whose results could be explained only if the electrons did, in fact, travel right through the bulk of a semiconductor, the linchpin to the practicality of Shockley’s idea. When they presented their findings to the rest of the group in their normal weekly team meeting, Shockley literally leaped from his seat and, for the first time, shared his idea for a “sandwich” transistor. It became painfully obvious to all that Shockley had been hoarding his secret for weeks and would likely have continued to do so for some time. In Shockley’s own words, “Shive forced my hand” [3]. Bardeen and Brattain sat stunned as they realized they had been deliberately kept in the dark.

Needless to say, Shockley was quick to file the now immortal patent for his “bipolar junction transistor” (Figure 8): U.S. patent 2,502,488, filed in June 1948 and issued 4 April 1950. Note the solo authorship. Shockley had the last laugh. Interestingly, the BJT patent also (almost casually) mentions the basic idea of the “heterojunction” bipolar transistor using a wide-bandgap emitter (Si), with a narrow-bandgap base and collector (Ge), anticipating the now enormously important field of bandgap-engineered devices. My own field. With both an idea and a basic theory of operation in place, it is ironic that the requisite art of making Shockley’s BJT did not yet exist, and thus, the BJT, ultimately a far more manufacturable and important transistor than the original point contact device, was not actually demonstrated until 12 April 1950 and in an article published in 1951 [9].

Figure 8. Page 1 of Shockley’s seminal BJT patent. (Source: U.S. Patent Office; used with permission.)

Brattain, Bardeen, and Shockley (justifiably, in my view) shared the Nobel Prize for physics in 1956 for their collective contributions in inventing their respective transistors (my guess is that they didn’t chum around afterward in a three-way backslapping celebration). Post transistor, Brattain went on to finish his career at Bells Labs, but Bardeen left Bell Labs in 1951, anxious to pursue different theoretical interests, culminating in a second Nobel Prize, for his theory of superconductivity.

After Bardeen and Brattain’s transistor patent was safely filed, on 17 June 1948, Bell Labs finally prepared to announce its landmark discovery to the world. The announcement was to be a two-pronged assault: 1) in the last week of June, Shockley called the editor of Physical Review and told him he was sending three papers that (hint, hint) needed to appear in the 15 July issue (this less-than-three-week publication cycle must be a record for a technical journal). One was the fundamental transistor paper [2], one offered an explanation of the observed transistor action (also by Brattain and Bardeen), and a third (now largely forgotten) was authored by Pearson and Shockley (go figure). 2) Bell Labs scheduled a major press conference in New York for 30 June. Not surprisingly, a mandatory military briefing was held first, on 23 June, with all in attendance forced by Bell Labs President Oliver Buckley to raise their right hand and swear that they would say nothing until 30 June (I’m not joking). The plot thickens. On Friday, 25 June, Admiral Paul Lee, chief of naval research, called Buckley and told him that the Navy had, in fact, already made a similar discovery, and he wanted to make the 30 June spectacle a joint Bell Labs–U.S. Navy announcement. Major panic attack! The next day, Shockley and company, armed with a cadre of patent lawyers in tow, met with the Navy, and after an intense line of questioning of engineer Bernard Salisbury by Shockley (you can easily visualize this), the Navy backed off, ultimately conceding that the Salisbury gadget was not, in fact, a transistor and that the Bell Labs team had been first. Whew!

The press conference went on as planned as a Bell Labs solo act. Sadly, however, with Brown making the formal announcement and the ever-entertaining Shockley selected for fielding all the reporter’s questions, the seminal contributions of Bardeen and Brattain were not prominently featured in the limelight. Reactions from the popular press to the transistor were decidedly lukewarm, but Bell Labs was not done. The next step (in hindsight, exceptionally shrewd) was to send out hundreds of letters, not to the press but to scientists, engineers, and radio manufacturers, inviting them to Bell Labs, on 20 July, for a demonstration of the new widget. The reception to this event was anything but mixed. Wowed by the discovery, requests for sample transistors began pouring in from all over the world. Kelly once again acted wisely, quickly forming a brand-new Bell Labs group, headed by Jack Morton, aimed explicitly at developing the technological infrastructure for manufacturing transistors in volume—the requisite “art,” if you will. By mid-1949, after significant sweat, over 2,700 “Type-A” point contact transistors had been produced and distributed to interested parties [5].

Fundamental problems with transistor reliability (at the time, little better than the vacuum tube competition) and control of performance parameters, however, soon forced Morton’s team to embrace Shockley’s BJT as the preferred transistor architecture for mass production (surely Shockley was smiling by now), and progress then came rapidly (Figure 9). Western Electric was the first company selected to manufacture transistors, paying a US$25,000 patent licensing fee for the privilege. All companies agreeing to pay this (in hindsight, ridiculously cheap) fee were invited to attend an exclusive “find out how we make ‘em” meeting at Bell Labs in the spring of 1952, and representatives from 26 U.S. and 14 foreign companies were in attendance. Nineteen fifty-three was proclaimed the “Year of the Transistor” by Fortune magazine. To place things in perspective, the combined transistor production from U.S. companies in 1953 was about 50,000 a month, compared with nearly 35 million vacuum tubes, but Fortune already glimpsed a bright future for the transistor and the potential for producing “millions a month” [5]. The selling price for a single transistor in 1953? About US$15.

Figure 9. The (a) first BJT and (b) first MOSFET. (Source: Alcatel-Lucent; used with permission.)

End of story? Nope. You might wonder what comes next that leads us from Ge back to Si and to produce the modern IC, Moore’s law, the microprocessor, and the world we know today. Alas, I am out of room for this issue. Stay tuned for the next installment. Trust me, it is a fascinating story, full of important takeaways.

Acknowledgment

Much of the text in this article owes a debt to the author’s book Silicon Earth: An Introduction to Microelectronics and Nanotechnology [1], which is intended for general audiences and used by the author in a course for undergraduates of all majors at the Georgia Institute of Technology.

Biography

John D. Cressler (cressler@ece.gatech.edu) is a Regents Professor and the Schlumberger Chair Professor in Electronics in the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA.

References

[1] J. D. Cressler, Silicon Earth: Introduction to Microelectronics and Nanotechnology, 2nd ed. Boca Raton, FL, USA: CRC Press, 2016.

[2] J. Bardeen and W. H. Brattain, “The transistor, a semiconductor triode,” Physical Rev., vol. 74, no. 2, pp. 230–231, Jul. 1948, doi: 10.1103/PhysRev.74.230.

[3] R. M. Warner Jr., “Microelectronics: Its unusual origin and personality,” IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2457–2467, Nov. 2001, doi: 10.1109/16.960368.

[4] R. M. Warner Jr. and B. L. Grung, Transistors: Fundamentals for the Integrated-Circuit Engineer. New York, NY, USA: Wiley, 1983.

[5] M. Riordan and L. Hoddeson, Crystal Fire (Sloan Technology Series). New York, NY, USA: Norton, 1998.

[6] T. R. Reid, The Chip. New York, NY, USA: Random House, 2001.

[7] P. K. Bondyopadhyay, P. K. Chaterjee, and U. Chakrabarti, “In the beginning [junction transistor] ,” Proc. IEEE, vol. 86, no. 1, pp. 63–77, Jan. 1998, doi: 10.1109/5.658760.

[8] W. Shockley, “How we invented the transistor,” New Scientist, vol. 21, pp. 689–691, Dec. 1972.

[9] W. Shockley, M. Sparks, and G. K. Teal, “p-n junction transistors,” Physical Rev., vol. 83, no. 1, Jul. 1951, Art. no. 151, doi: 10.1103/PhysRev.83.151.

Digital Object Identifier 10.1109/MED.2023.3267740

Date of current version: 28 June 2023

Working for William Shockley - In Memoriam: Adolf Goetzberger

Joachim N. Burghartz

©SHUTTERSTOCK.COM/MICHAEL VI

William Shockley is one of the inventors of the first transistor, which was demonstrated 75 years ago. He is also the founder of Shockley Labs in Palo Alto, California, the actual origin of Silicon Valley. This article sheds light on his personality as described by his employee and colleague Adolf Goetzberger during 1958–1963.

Much has been written about Bardeen, Braittain, and Shockley and their demonstration and understanding of the physics of the first transistor in 1947 and 1948. This includes articles on their quite-different personalities. It is also well known that Shockley Labs, founded by Shockley with financial support from Beckman Instruments, Inc., although not successful itself, gave birth to what later became Silicon Valley. The so-called “traitorous eight,” among them Gordon Moore, Bob Noyce, and Jean Hoerni, who left Shockley Labs in 1957 after a disagreement about the technical direction of the company and having coped with Shockley’s management style, founded Fairchild, which later became Intel. They made room for new scientific staff, such as Goetzberger, whom I had the pleasure of meeting after receiving the J.J. Ebers Award from the IEEE Electron Devices Society in 2014 as the second German to do so, following Goetzberger in 1983. The stories he told me about his time with Shockley were very interesting and so off the beaten path that I tried to engage him for a contribution to this inaugural issue of IEEE Electron Devices Magazine. However, Goetzberger, at the time nearly 95 years of age, was not comfortable writing an article by himself, nor going through with an interview. Instead, I found a solution by putting together an article about Goetzberger’s work with Shockley, using the information I had from that meeting with him in 2015, but also from an interview by Nebeker [1], from an article by Magoun [2], and from Goetzberger’s memoirs, which were published in a booklet in 2020 [3].

Goetzberger studied physics in Munich, Germany, during difficult times in postwar Germany, working first for Siemens in Munich on the development of germanium transistors; although, as he said, the work atmosphere was not all that exciting:

The work mainly consisted of getting literature from the United States and then trying to repeat what they had done before. This was, in the long run, not very satisfactory to me. Some of my colleagues had already gone to America, and I decided that this would be the right thing for me to do if I wanted to develop professionally [3].

A friend who worked for a Beckman Instruments subsidiary in Munich told him about Shockley Labs, which had been founded a couple of years earlier in Palo Alto. The intended product of that company was a complicated, four-layered diode invented by Shockley as a replacement of the mechanical relay used in telephone systems, which could never be fabricated with sufficient yield. Goetzberger did not yet know about those difficulties and decided to apply for a position. However, Shockley Labs was already fully staffed and Goetzberger’s application was rejected. A bit less than one year later, he received a phone call about Shockley being in Munich and that he wanted to see him. This was shortly after the traitorous eight had quit Shockley Labs. Shockley was assisted in the job interview by his wife, a psychologist, who was quite influential about whom Shockley would hire, as Goetzberger later found out. During the interview, Goetzberger explained to Shockey about a special type of drift transistor he invented:

We had a very interesting talk and he asked me all sorts of questions. But what really made the difference was that, from the literature, I had decided I was going to propose a new type of transistor, which had certain advantages [1], [2], [3].

This convinced Shockley, and he got the job offer. It was a tough personal decision for Goetzberger to move to the United Stated, having never before traveled overseas. The company he joined was very small, with only three scientists and roughly 10 technicians. The technology equipment was put up without any apparent system in a dirty environment. He shared an office with Kurt Hübner, a Swiss, and with Chi Tang Sah who, together with Wanlass, later pioneered CMOS. Shockley, an excellent theoretician, was complemented by Goetzberger, a gifted experimentalist, so the two got along very well. Shockley put Goetzberger on nonideal p-n junctions, which was the major issue at that time. This was not a surprise because of the dirty lab conditions. Metal contamination caused nonideal and very leaky junctions. Goetzberger discovered that metal contaminants could be diffused away from the junctions toward a phosphor glass layer at the surface of the silicon substrate, with perfectly ideal junctions as a result. He thus invented the gettering technique in semiconductors, a very important advancement of early semiconductor technology.

(Right) Adolf Goetzberger and Joachim Burghartz meeting in Freiburg, Germany, in 2015.

Goetzberger described Shockley’s character as being difficult for many of his employees in two ways. First, after having been a part of the pioneering team demonstrating the first transistor at Bell Labs in 1947 and 1948, and after having received the Noble Prize in Physics together with Bardeen and Braittain in 1956, he developed the ambition to become a successful businessman rather than continuing his career as a scientist. A statement Goetzberger frequently repeated was, “I have long enough read my name in Physical Review, but now I want to see it in [the] Wall Street Journal” [3]. Second, his management style was such that he always started out with the theory of a device and then asked his people to prove it experimentally. Because of that, according to Goetzberger, he was impatient and demanding: “He invented new devices much faster than we could realize them” [1], [2]. Quite often, he got occupied with a device that had little chance of becoming a yieldable product, such as the four-layer diode mentioned earlier. This was difficult for his scientific staff to tolerate, as in their view, this repeatedly put the company’s future in question. Those aspects of his personality eventually led to the departure in 1957 of the traitorous eight, who wanted to produce and sell transistor switches. As Goetzberger recollected it, “They had had some disagreements with Shockley about which devices to develop. Obviously, they were right because they were very successful” [1], [2].

In 1960, Shockley Transistor Corporation, as Shockley Labs was formally called, was sold to Clevite Semiconductors. Shockley had to resign and joined Stanford University as a university professor but stayed on as an advisor to Clevite. Goetzberger was assigned to take over part of Shockley’s former scientific management tasks. The company now aimed at simple diode rectifiers produced in large quantities and had little appreciation for the scientific interests and excellence of the scientific staff. So Goetzberger, along with his wife, moved to New Jersey to work for Bell Labs. The work conditions at Bell Labs were magnificent, a researcher’s heaven. He worked with Ed Nicollian on MOS surface physics, and investigated minority carrier lifetime effects in MOS structures when working in the group of George Smith. Smith, together with Bill Boyle, later built on this and other basic investigations to invent the CCD, for which they received the Noble Prize in Physics in 2009.

Goetzberger returned to Germany in 1968 to become director of the Fraunhofer Institute for Applied Semiconductor Physics in Freiburg. However, he still had his dream about leveraging semiconductors for photovoltaics, which he shared with another German who had joined Shockley Labs one year after Goetzberger: Hans Queisser. Goetzberger was able to convince Fraunhofer to found the Fraunhofer Institute for Solar Energy in Freiburg, which has become one of the leading research institutes in photovoltaics worldwide.

While this article went through a peer review process, I received the sad news that on 24 February 2023, Goetzberger passed away in Freiburg. I consider it a fortunate coincidence that in January, this article was on his desk and was reviewed by him, as I learned from his assistant. The electron device community, and photovoltaic community in particular, has lost one of their great pioneers.

Biography

Joachim N. Burghartz (burghartz@ims-chips.de) is with Institut für Mikroelektronik Stuttgart (IMS CHIPS), Allmandring 30a, 70569 Stuttgart, Germany.

References

[1] A. Goetzberger, Mein Leben: Ein Leben Für Die Sonne Und Wie Es Dazu Kam. Erlangen, Germany: Verlag Solare Zukunft, 2021.

[2] F. Nebeker, Oral-History:Adolf Goetzberger, IEEE History Center, Piscataway, NJ, USA, Sep. 1994.

[3] A. B. Magoun, “There, and back again: How Adolf Goetzberger got to solar energy,” Proc. IEEE, vol. 103, no. 3, pp. 476–481, Mar. 2015, doi: 10.1109/JPROC.2015.2399072.

Digital Object Identifier 10.1109/MED.2023.3265461

Date of current version: 28 June 2023

Echoes of the Past: A Journey to Re-Create the Invention of the Transistor and the Earliest Transistor Circuit: Appreciating the Technical Challenges and Genius of Bardeen and Brattain

Robert B. Kaufman, Benjamin Kesler, Thomas O’Brien, Patrick Su, John M. Dallesasse

©SHUTTERSTOCK.COM/FRANCESCO CANTONE

The invention of the first transistor—the point-contact transistor—by John Bardeen and Walter Brattain in 1947 marked a pivotal moment in electronic technology, and arguably an inflection point in human history. To honor the transistor’s 75th anniversary, this work presents a historical perspective of the invention of the point-contact transistor and efforts to fabricate replica devices. Rediscovery of contact forming methods from the days of crystal rectifiers are required to produce point-contact transistors with any gain. The history and accounts of Bardeen and Brattain’s work is traversed to help further inform the design parameters and test protocols needed to create a replica device. Finally, a working point-contact transistor is made and used to power a replica of a famous demonstrator circuit used to showcase the first transistor: the “Bardeen music box” or “oscillator-amplifier box.”

Introduction

We sometimes forget that there is art in technology, and that making things work is as much knowing the art as it is understanding the physics. Discovery of the transistor effect in point-contact devices by Bardeen and Brattain [1], [2], [3], [4] represents one of the most impactful discoveries in human history. Harnessing the power of electrons and holes in semiconductors has been likened in impact to humanity’s harnessing of fire [3]. If we think of the global transformation that has been brought about by modern electronics, the merit of this analogy is clear. It may even be perceived to understate the impact if we consider the compressed time frame in which modern electronics has transformed the planet: 75 years as opposed to millennia. If today we are like ancient man holding a stick of fire, it is incomprehensible to project what the future may hold.

Bardeen and Brattain’s point-contact transistor, and Shockley’s refinement into the junction transistor, came about because the right people were looking at the right problem at the right time; so it goes with many important discoveries and inventions. Bardeen was arguably one of the greatest condensed-matter physicists of the last century as his two Nobel Prizes in Physics attest. Brattain was a talented experimentalist who knew the art but also the physics behind it. The fact that Brattain and Bardeen shared an office at Bell Labs created a perfect convergence where art and science met, and the unusual and unexpected gain in this three-terminal device could be observed and explained. Yet even getting to this point was an event many decades in the making. First were the crystal rectifiers, curious devices that passed current in one direction but not the other. Braun discovered these in the late 1800s by scratching a metal wire on a piece of galena (lead sulfide). The usefulness of these devices in wireless telegraphy led to Braun and Marconi sharing the 1908 Nobel Prize [5]. Despite being useful, these devices were not understood. The advent of modern physics and the emerging understanding of the quantum nature of matter and wave-particle duality led to work by physicists such as Sommerfeld, Mott, and Schottky who put forth theories of metals and metal-semiconductor contacts that could explain effects such as rectification. The unique capability of such devices to operate at much higher speeds than electron tubes, coupled with a need for high-speed devices driven by World War II’s parallel battle for technical supremacy, led to advances in materials science that produced higher-quality semiconductors suited for these high-speed rectifiers. “High back voltage germanium” was created to improve rectifier performance, and this material was in Brattain’s hands when the work on trying to find three-terminal semiconductor-based devices for switching and amplification was taking place. Without this material, it is fairly safe to postulate that the discovery of the transistor would not have occurred in 1947. Perhaps it would have eventually occurred, but the world today would be a different place in any case.

When it was proposed during the meeting of the Electron Devices Society committee coordinating efforts to commemorate the 75th anniversary of the invention of the transistor that we re-create the demonstration of the point-contact transistor, it was imagined to be an easy thing. The art has progressed, after all, to a point undreamed of by Bardeen and Brattain in those early days. At the same time, as new pathways are forged, the old pathways are sometimes forgotten and need to be rediscovered. So, it was here, where the art held in a few simple sentences in Bardeen and Brattain’s original paper related to “contact forming,” which would have been obvious to readers at that time, proved to be one of the barriers that needed to be overcome.

The Point-Contact Transistor

Bell Telephone Laboratories in the mid-1940s was fertile ground for work on semiconductor devices. Mervin Kelly, believing in the potential use of semiconductors in the telephone system, had established a group to work on solid-state electronics. Brattain, who had worked on copper oxide rectifiers in the 1930s, was a part of that group when Bardeen joined in 1945. Tasked by Shockley to work on field-effect devices, Brattain began to observe curious effects in the devices with which he was experimenting. Engaging Bardeen as a partner in the effort to work on and explain results as well as chart new experiments, Brattain ultimately wrapped a nonconductive wedge with gold foil, separated the foil at the tip of the wedge with a razor blade, and rigged an apparatus to hold the wedge against the piece of high back voltage germanium. An early reproduction of the device is shown in Figure 1. On 16 December 1947, amplification was observed, and the transistor was born.

Figure 1. An early reproduction of the first point-contact transistor. This replica is on display at the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign (on loan from Prof. Jont Allen).

Explaining transistor operation was another matter. The same physical effect that enabled the creation of earlier rectifiers would be the critical element for the point-contact transistor: the band bending at the surface of a semiconductor either due to the interface with a metal contact or natural surface states. If this effect is strong enough, it is possible for an inversion layer to form at the surface of the semiconductor crystal, meaning that the dominant carrier type switches. In the case of the n-type germanium used for the first point-contact transistors, in the bulk of the crystal, negatively charged electrons makeup the majority carriers. But at the surface, due to a disruption of the periodic nature of the crystal, states form, which make holes, a positive charge carrier that can be thought of as a lack of an electron, the dominant carrier [6]. This thin, p-type layer at the surface enables the operation of the point-contact transistor and, although the exact mechanism was not verifiably understood, early studies on the device provided some explanation [2], [6]. This band bending and inversion was described in the seminal paper by Bardeen and Brattain that immediately followed their paper describing transistor action [1], [2], and is shown in Figure 2.

Figure 2. A band diagram for n-type germanium with a thin, p-type region formed at the surface due to surface state pinning [2]; this was how Bardeen and Brattain originally described the effect that enabled the p-type hole source in the point-contact transistor. (Source: [2]; Reprinted Figure 2 with permission from W.H. Brattain and J. Bardeen, Phys. Rev., vol. 74, no. 2, pp. 232, 1948. © 2023 American Physical Society; https://dx.doi.org/10.1103/PhysRev.74.23.)

Emitter and collector contacts are made on the thin, p-type layer at the surface, with the base contact on the n-type bulk substrate from the bottom of the sample. The emitter is positively biased with respect to the base to inject current in the form of holes into the p-type layer. The collector is negatively biased, which attracts the positively charged holes injected from the emitter, contributing to a portion of the collector current that exits. In addition, a mechanism between the base and collector attracts electrons out of the collector contact to the n-type base region of the device. As this is an inflow of negative charge, this provides an additional positive current out of the collector in addition to the hole current from the emitter. With the two currents combined, the collector current acts to amplify the emitter current, and hence, the device produces a positive gain known as the alpha of the transistor. An illustration of an active point-contact transistor with the general indication of current flow and carrier direction is presented in Figure 3. It should be noted that this mechanism is slightly different from the transistor effect in the junction transistor, where the minority carrier injection from the emitter into the base is captured by the collector and the base current is largely serving base recombination.

Figure 3. An illustration of an active-mode point-contact transistor with a positive emitter bias and negative collector bias. The current directions of each terminal are indicated and the rough propagation of carriers contributing to the collector current are shown.

History Repeats Itself—Following the Path of Discovery

At the time the point-contact transistor was demonstrated, it was not possible to order high-quality semiconductor wafers from your vendor of choice. The piece of germanium used by Brattain was provided to Bell Labs by Purdue, one of the few groups working on these materials at the time [4]. It had seen several other experiments before its use to make the first transistor. In an interesting parallel, as a consequence of supply-chain issues attributed to the COVID-19 pandemic, germanium, having a conductivity level and type similar to that which was used by Brattain, was likewise difficult to obtain when our efforts began. For the work on recreating a point-contact transistor, an antimony-doped n-type germanium wafer was obtained with a resistivity in the range of 1–10 Ω-cm, which was on the lower end of the reported ideal resistivity range [1]. At a high level, very little is needed to be done to produce a functional point-contact transistor once the germanium crystal is obtained. One could even learn how to make his or her own at home by modifying certain commercial diodes from a 1950s magazine article [7]. The original device design simply consisted of two tungsten or phosphor bronze wires mounted closely together on the surface of a block of germanium to form the emitter and collector contacts [1]. The base contact is made from a metal connection to the backside of the germanium block. To replicate this, for our own attempt at the point-contact transistor, a germanium wafer was separated into pieces approximately 1 cm × 1 cm in size. Initially, standard tungsten probe tips typically used for general device electrical characterization were used for the emitter and collector contact (although it was soon discovered that different contact methods had to be explored to make a quality transistor). These tips were mounted on micromanipulators with three linear movement axes to allow micrometer-level control of their position. Referencing the spacing of the original point-contact transistor demonstration, roughly 40 µm between split gold strips on an insulating wedge [1], [4], the tungsten probe tips for our transistor were spaced as close as 10-µm apart, with the hope that the closer spacing would improve performance. The base contact on the backside of the thin, 600-µm-thick wafer is made from evaporated nickel and gold, which is contacted by the metal stage the sample rests on during testing.

In theory, our point-contact transistor was complete and all that was left was to characterize it, which was done using a semiconductor parameter analyzer to sweep values and measure the voltages and currents across and through the three device terminals. The result was a transistor effect, but just barely, as demonstrated by the common-base transistor curve measured in Figure 4. No gain was observed in either the emitter or base current; the collector current was smaller than both. Although no base gain is expected for a point-contact transistor, the lack of emitter gain, termed alpha, was disappointing. This was indicative of two potential issues: the supposed inverted p-type layer at the surface was smaller than expected, and the path between the collector contact and the base was too resistive. This would lead us on a journey to rediscover old methods for creating point-contact transistors, from contact preparation methods poorly understood and no longer used in modern transistor devices, to earlier contact solutions that Bardeen and Brattain explored in their quest to fabricate the first transistor.

Figure 4. A plot of common-base transistor curves measured on an old Tektronix 577 Curve Tracer, demonstrating the transistor behavior of our first attempt at the germanium point-contact transistor; this device consists of two tungsten probe tips acting as the emitter and collector terminals, and a backside Ni/Au layer for the base terminal.

One key element of the point-contact transistor preparation is the collector-contact formation. Despite not being used for Bardeen and Brattain’s very first gold-wedge-based transistor, this process became the standard for production transistors and was used for the results in the first publication of the device [1], [8]. A process common back in their time for the fabrication of germanium high-voltage crystal rectifiers, contact forming is done by passing a large amount of current over a short pulse between the point contact and backside contact, lowering the resistance between the two. For the point-contact transistor, this was done between the collector and base contacts. The exact mechanism for the improvement of gain in point-contact transistors is not fully verified. Different hypotheses, including some strong ones from Shockley, postulate a potential conversion of the n-type region near the probe to a larger, permanent p-type region or, alternatively, an introduction of positively charged trap states that would attract electrons from the collector contact [5]. Whatever the cause, this old process was a critical element in enhancing the gain in the point-contact transistor design. The contact forming came with some challenges when determining how to implement it. Various methods for achieving contact forming have been reported with no clear best method, with each sharing in common an issue with low yield [7], [8], [10]. The general method involved sending a high reverse-current pulse through the base and collector terminals, less than 1 A, that required in the range of 30–300 V. One reported method for performing this forming injection includes charging a capacitor and then switching it to the point contact and quickly discharging it across the base-collector terminals [10]. Another method would involve specialized equipment to control pulsed voltage signals across the contacts, either dc reverse bias or ac forward and reverse injections [8]. This second method is the one performed for our point-contact transistors as it allowed more control of the contact forming process without the need for high-voltage capacitors or switches and is likely also the method used by Bardeen and Brattain as it was reportedly used by Bell Labs, where they did their research [1], [8]. This was attempted with an Hewlett-Packard 214B 100-V pulse-generator and a Tektronix 577 Curve Tracer, which enabled up to 1,000-V, 300-µs-long pulses, although it was limited to 100 W of maximum power. Various forming attempts were done using the tungsten probe contacts with pulsed voltages up to 200 V, and although some improvements were had, especially in the stability of the curves, the devices still had a gain below one; Figure 5 shows the comparison of a point-contact transistor before and after contact forming.

Figure 5. A comparison of the emitter gain curves of the gold pad/tungsten probe point-contact transistor before and after collector forming.

With just the collector forming not producing close to the results of the original point-contact transistor, the next step was to find the best contact configuration. Coincidentally, this set of experiments would lead back from the first two-wire point-contact transistor to some of Bardeen and Brattain’s early experiments preceding it. The next contact design explored was the gold-wedge point-contact transistor, their first demonstration of a solid-state transistor with positive power gain. The main motivation for trying this contact design was to test whether using gold over tungsten would offer any improvements. Using a Teflon wedge, gold foil, and Kapton tape, a similar setup as Bardeen and Brattain’s original discovery attempt was made, as depicted in Figure 6(b). The gold was wrapped tightly around the corner of the wedge and affixed by the tape. It was then thinly slit along the edge with a scalpel blade, separating the two contacts. Now it was reported that Brattain had slit the gold and filled the gap with a wax, leaving a very thin, 40-µm spacing [4]. Unable to replicate his precision, a trial-and-error process of slightly folding back the edge of the separated gold was done until the two contacts were no longer shorted. The final gap measured ∼ 200–250 µm, much larger than Brattain’s. Nonetheless, small transistor effects were seen with this gold-wedge contact setup in our own point-contact transistor, although the output stability was poor. Similar to what Bardeen and Brattain were said to have encountered, the exact mount position of the wedge contact was inconsistent and would involve some fidgeting to achieve the proper contact [4]. There was one promising, although incredibly unstable, measurement of the wedge point-contact transistor that occurred, likely due to a lucky positioning of the mount that aligned the two contact strips close together. However, no repeated measurements were able to capture the same performance.

Figure 6. A collage of the various point-contact transistor setups we attempted. (a) Two tungsten probes set up as an emitter and collector contact for a point-contact transistor. (b) A gold-wedge point-contact transistor setup. (c) A gold-wrapped scalpel as an emitter and a tungsten probe as a collector setup. (d) Evaporated gold pads set up with a formed collector contact over a degraded pad.

To solve the issues with inconsistent contacts, approaches that involved aligning probes or other connections with the micromanipulators were strictly used after the wedge attempts, as demonstrated in Figure 6. These methods enable precise and close spacing between the emitter and collector contact, which was proving to be a critical dimension for our point-contact transistor given the germanium crystal with which we were working. First, numerous attempts were done to re-create the line contact in replacement of the wedge with both tungsten and gold and mixed contacts. This included gold-wrapped flat scalpels, sideways-mounted tungsten probe tips, and gold-wrapped tungsten probe tips. Collector-forming methods, from 50 to 200-V reverse bias and 300-µs-long pulses, were attempted with these different contact methods as well. For most of these attempts, performance was on par or worse compared to our first dual-tungsten-probe point-contact transistor tests. The attempts where the collector featured a longer, line-type contact instead of a point had particularly poor results, whereas when the emitter contact was a larger, gold contact and the collector a narrow, tungsten point contact, the highest gain measurement was taken of this set. Yet again, this measurement was not capable of being repeated, a common theme for our point-contact transistor attempts.

One last idea to enable consistent contacts was to not use the probes as the contact material but instead deposit small pads of gold directly onto the surface such that the contact is permanently on the surface and can provide the probing consistency being sought. This approach was yet again going backwards in the history of Bardeen and Brattain’s transistor attempts. This deposited gold contact method was indeed the first, and accidental, discovery of the transistor effect on the n-type germanium [4], [11]. Although trying to create something more akin to a field-effect transistor, they deposited small circles of gold over what they thought was an insulating oxide layer and used a tungsten wire as the collector contact [4], [11]. What they initially failed to realize is that the oxide had been washed off, so the gold was directly contacting the surface of the p-type inversion layer, enabling a demonstration of the transistor effect (described as increased reverse-bias current through the collector from emitter injection) [4], [11]. Although their attempt at this did not produce any gain, our hope was that by forming the collector contact we could make a point-contact transistor with positive gain and a more consistent contact. To do this, gold squares were evaporated on the germanium piece and patterned by a lithographic liftoff process. Indeed, the results were more consistent, producing much more stable transistor curves, but without forming the collector contact there was no gain, as expected at this point. Many attempts at forming the collector gold pads were done, trying both dc and ac methods. After pulsing 70-V ac (to enable both forward and reverse current injection) across the collector metal pad and base contact, it had initially looked like this device would be destroyed; the collector pad had been visually damaged. Yet, when the transistor curve measurements were taken, the device produced the highest gain thus far. The collector forming had made significant improvement of the gain of the device emitting a higher collector current at a collector bias of 10 V than a bias of twice that, 20 V, for the nonformed contact. And thus, with a 50 µm × 50-µm gold pad acting as the emitter contact, and a formed tungsten probe spaced approximately 20-µm away as the collector, a point-contact transistor with positive gain and a stable output was made.

Chasing Alpha—Benchmarking Relative to Bardeen and Brattain

To compare the results of our point-contact transistor, the same measurements reported on Bardeen and Brattain’s original transistor paper published in 1948 were taken [1]. The transistor reported in this article is not the first gold-wedge device but is instead a more refined device that likely utilized two phosphor bronze probes placed close together, with the collector lead likely formed by 30-V ac pulses [1], [8]. Bardeen and Brattain characterized this device by grounding the base of the transistor, applying a positive voltage on the emitter (V_e), and applying the negative voltage on the collector (V_c). Two different measurements were done in the original paper; one where V_c is fixed and one where V_e is fixed. This measurement was replicated on our own gold-pad/tungsten-probe point-contact transistor, and the data are presented adjacently to Bardeen and Brattain’s for comparison in Figure 7(a) and (b). These tangles of curves can be hard to decipher at a first glance, especially as they are atypical for modern measurements used to characterize transistors (after all, this is the very first transistor demonstrated, so there are no standards to reference). But for the point-contact transistor, characterized by its emitter gain alpha, these plots make the most important feature easy to identify. Bardeen and Brattain defined the alpha of a transistor by the change of the collector current for some change in the emitter current (dI_c/dI_e), which is represented by the slopes of the collector-current versus emitter-current plots presented here; the more vertical the line is, the higher the alpha. This gain of emitter current is the key ability of the transistor, which makes it useful for circuits such as amplifiers or oscillators.

Figure 7. (a) An I_c versus I_e plot of Bardeen and Brattain’s first published point-contact transistor, demonstrating the alpha gain of the device for either fixed-emitter or fixed-collector voltages [1]. (b) The same plot and parameters measured for our own point-contact transistor attempt, using a 50 µm × 50-µm gold pad as the emitter and a formed tungsten probe as the collector. (Source: [1]; Reprinted Figure 7(a) with permission from J. Bardeen and W H. Brattain, Phys. Rev. vol. 74, no. 2, pp. 230, 1948. © 2023 American Physical Society; https://dx.doi.org/10.1103/PhysRev.74.230.)

When comparing the data from Bardeen and Brattain’s original published transistor, very similar electrical behavior is seen between theirs and our point-contact transistor device. When the emitter voltage is fixed (solid lines), both ours and the original transistor show high alpha gain of more than two. One key difference is that ours demonstrates this large gain for even higher values for V_e , while the original transistor starts to see a reduced gain. This is due to poor current injection in our transistor, leading to smaller amounts of injected emitter current when compared to similar voltages for the original device. For example, in the original transistor, an emitter voltage of 0.7 V injects 2 mA of current at 0 mA of collector current, while for our transistor, only 0.3 mA is driven. For the measurements when collector voltage is fixed (dashed lines), closer trends at high biases are seen but with much worse gain at low voltages for our transistor. When biasing the device to −5 V, very little differential emitter gain is seen, with the slope of the curve being almost flat, indicating an alpha of less than one, whereas the original transistor had more noticeably positive slopes. At the 10- and 20-V reverse-bias collector measurements, our transistor starts to match the performance of the original transistor with an alpha of nearly 1.2, even if the magnitude of total current still trails that of Bardeen and Brattain’s transistor. Despite some of the differences, our transistor was still able to demonstrate comparable alpha gain to the first transistor. This gain value was an important milestone to achieve as it was a goal of the project to not just re-create a point-contact transistor but to also use one to drive the oscillations in a music “box” circuit, such as Bardeen had as a demonstration of the first transistor.

A More Interesting Demo—Lessons From the Oscillator-Amplifier Box (“Bardeen Music Box”)

At some point, it was determined that a simple, portable apparatus was needed to demonstrate the transistor. Three boxes were made by engineers at Bell Labs to demonstrate oscillator and amplifier uses of the transistor, the so-called “oscillator-amplifier boxes.” Some of the original “type A” transistors were used to create these boxes, making them likely the oldest transistor-based circuits in existence. Only one of these boxes is known to still exist, it being in the permanent collection at the Spurlock Museum at the University of Illinois at Urbana-Champaign. Bardeen is shown holding one of the original boxes in Figure 8, and a photo of the interior of the box is presented in Figure 9.

Figure 8. Bardeen holding his music box, which was one of the first circuits to use the point-contact transistor; one transistor was used to drive an oscillator circuit and one was used as an amplifier. (Source: University of Illinois Board of Trustees.)

Figure 9. An image of the circuit inside Bardeen’s original music box, which we annotated as part of the process of tracing and relearning how it functioned.

The final test of our point-contact transistor was to see whether it could be used to re-create Bardeen’s music box. At the time, the key advantage of the point-contact transistor in this portable music box is its small size and “instant” turn on, replacing the role of more bulky vacuum tubes that required time to warm up [11]. With access to Bardeen’s original music box during a restoration project, the original circuit was mapped out [12]. Having just discovered the transistor, all the components in Bardeen’s box were designed for vacuum tube circuits, hence the use of a 45-V battery even though suitable gain could be provided from the transistor at lower voltages [11]. Using measured values for the capacitors and resistors from the original music box, we reconstructed the oscillator part of the circuit from modern components on a breadboard. Our point-contact transistor was contacted and jumpered into the circuit. To provide the 45-V source, an Agilent E3647A dc power supply was used instead of a battery. The result was a sustained oscillation that can then be passed to a buffer amplifier, driving an 8-Ω speaker to produce a constant tone. Although in the Bardeen music box this amplifier portion of the circuit also utilized a point-contact transistor (labeled T2 in the image of the box), we opted to use a modern chip. Different buttons on the breadboard would reroute the circuit through different capacitors, altering the resonant frequency of the LC bank and, in effect, playing different notes. The apparatus used is shown in Figure 10.

Figure 10. An example measurement of the sinusoidal output of the Bardeen oscillator circuit remade with modern components and using our point-contact transistor setup as the gain provider.

The schematic of the Bardeen oscillator circuit is shown in Figure 11. Although it looks complicated, it operates under a couple of basic principles. The array of capacitors seen on the right is connected to the circuit through a switch, which forms a loop with the inductor. This is referred to as an LC bank and has a natural oscillating frequency of current that usually fades to zero due to resistive elements in the circuit. Some sort of gain is required to overcome this loss and sustain this oscillating current. This is where the point-contact transistor comes in. The inductor in the LC bank is coupled to a second coil (like a differential-mode choke), which induces a copy of the oscillating current into the emitter of a point-contact transistor. As the transistor produces an alpha gain of the emitter current, this oscillating signal is amplified by the base current and exits the collector, feeding back into the LC bank loop, thus providing the extra power to overcome inherent losses and sustain the oscillations. The output is measured across the coupled inductor and resembles a sine wave with a specific frequency. When this output is connected to a speaker drive and speaker, a solid tone is heard. By pressing different buttons, switching said capacitor is a part of the LC bank, different frequencies, and thus tones, are produced and music can be played. The frequencies produced in the original Bardeen box and our re-creation range from just under 3 kHz to below 5 kHz.

Figure 11. The Bardeen oscillator circuit as traced from one of his original music boxes with an inset table of measured component values.

How Dry I Am

Nick Holonyak Jr., John Bardeen’s first graduate student and “father of the LED,” would often recount an early seminar given by Bardeen after Bardeen was recruited to the faculty at the University of Illinois at Urbana-Champaign. Bardeen, in his quiet way, described the physics of transistor operation. He then flipped the switch on the “Oscillator-Amplifier Box” and immediately played the tune “How Dry I Am” using keying notes taped to the top of the box (Figure 12).

Figure 12. The notes and lyrics for playing “How Dry I Am” on Bardeen’s music box.

“I nearly fell out of my chair,” Holonyak would exclaim when reciting this story. Holonyak immediately saw what had captured the world’s attention: a device that did not need to warm up prior to operating, that would provide near-instantaneous service in whatever application was demanded. Holonyak left the tube group he was working in as a graduate student to join this new professor. His fellow students thought he was crazy; electron tubes were ubiquitous at that time. History has shown that Holonyak was right.

Final Observations

The effort to re-create a point-contact transistor and one of the earliest transistor circuits proved to be an interesting journey through the history of technology. Guided by accounts of Bardeen and Brattain’s efforts and our earlier work to understand the operation of Bardeen’s oscillator-amplifier box, we were able to retrace their steps and create working devices and circuits. Despite our best efforts, we could not match their performance, however, as we were limited by the higher doping density of our germanium. Interestingly, a few questions still remain about the operation of the early point-contact transistors. The creation of a transistor in an n-type sample with no intentional p-doping is enabled by an interesting interplay between surface states, Fermi energies, and the effect on the germanium crystal of “contact forming.” The latter process, especially, left a few unanswered questions, both then and now. The advent of the superior junction transistor ultimately made these questions moot, but the most important discovery, minority carrier injection, had been made.

Acknowledgment

We thank the Spurlock Museum at the University of Illinois at Urbana-Champaign for the preservation of the “Bardeen Music Box” and for granting access to it for transcription of the circuit. Specifically, appreciation is extended to Christa Deacy-Quinn and Travis Stansel for their assistance in accessing the original box and providing related images.

Biographies

Robert B. Kaufman (rbkaufm2@illinois.edu) is with the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. He is a Member of IEEE.

Benjamin Kesler (benjamin.kesler@lumentum.com) is currently with Lumentum Operations, limited liability corporation, San Jose, CA 95131 USA, but was with the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign for his contribution to this work.

Thomas O’Brien (thomas.obrien@intel.com) is currently with Intel Corporation, Hillsboro, OR 97124 USA, but was with the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign for his contribution to this work.

Patrick Su (patrick.su@apple.com) is currently with Apple Inc., Cupertino, CA 95014 USA, was with the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign for his contribution to this work.

John M. Dallesasse (jdallesa@illinois.edu) is with the Holonyak Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. He is a Fellow of IEEE.

References

[1] J. Bardeen and W. H. Brattain, “The transistor, a semi-conductor triode,” Phys. Rev., vol. 74, no. 2, pp. 230–231, Jun. 1948, doi: 10.1103/PhysRev.74.230.

[2] W. H. Brattain and J. Bardeen, “Nature of the forward current in germanium point contacts,” Phys. Rev., vol. 74, no. 2, pp. 231–232, Jun. 1948, doi: 10.1103/PhysRev.74.231.

[3] M. Riordan and L. Hoddeson, Crystal Fire. New York, NY, USA: Norton, 1997.

[4] L. Hoddeson and V. Daitch, True Genius: The Life and Science of John Bardeen. Washington, DC, USA: Joseph Henry Press, 2002.

[5] “The Nobel prize in physics 1909,” Nobel Prize Outreach AB, Stockholm, Sweden, Jan. 2023. [Online] . Available: https://www.nobelprize.org/prizes/physics/1909/summary/

[6] J. Bardeen and W. H. Brattain, “Physical principles involved in transistor action,” Phys. Rev., vol. 75, no. 8, pp. 1208–1225, Apr. 1949, doi: 10.1103/PhysRev.75.1208.

[7] P. B. Helsdon, “Home-made transistors,” Wireless World, vol. 60, pp. 20–23, Jan. 1954.

[8] H. C. Torrey and C. A. Whitmer, “Chapter 12: High-inverse-voltage rectifiers,” in Crystal Rectifiers, S. A. Goudsmit, L. B. Linford, J. L. Lawson, and A. M. Stone, Eds. New York, NY, USA: McGraw-Hill, 1948, pp. 361–397.

[9] W. Shockley, “Theories of high values of alpha for collector contacts on Germanium,” Phys. Rev., vol. 78, no. 3, pp. 294–295, May 1950, doi: 10.1103/PhysRev.78.294.2.

[10] B. N. Slade, Factors in the Design of Point Contact Transistors. Harrison, NJ, USA: Radio Corporation of America, 1953.

[11] N. Holonyak, “John Bardeen and the point-contact transistor,” Phys. Today, vol. 45, no. 4, pp. 36–43, Apr. 1992, doi: 10.1063/1.881336.

[12] R. Monahan, “Bardeen’s ‘Music Box’: The notes of technological innovation play again,” Elect. Comput. Eng., Univ. Illinois, Urbana, IL, USA, Mar. 2019. [Online] . Available: https://ece.illinois.edu/newsroom/news/4184

Digital Object Identifier 10.1109/MED.2023.3257144

Date of current version: 28 June 2023

Hermann K. Gummel and His Unique Legacy in the Field of CAD Technology for Integrated Electronics: Six Former Coworkers Remember and Reminisce

Ken Haruta, Shiuh-Wuu Lee, Colin McAndrew, Bernd Meinerzhagen, Laurence W. Nagel, E. James Prendergast

©SHUTTERSTOCK.COM/IAROSLAV NELIUBOV

Hermann K. Gummel made numerous fundamental and high-impact contributions to the IC industry, in particular to IC design technologies. One of the most notable was in the domain of bipolar transistors: Today nobody designs bipolar transistors, or circuits based on bipolar transistors, without using the eponymous “Gummel plot.” An early pioneer of the IC industry, Hermann passed away in 2022, the year of the 75th anniversary of the invention of the transistor. Here, six of his former coworkers review some of Hermann’s most significant and wide-reaching contributions, to bipolar transistor modeling in particular and to computer-aided IC design technology in general, and reminisce about his warm and exceptional personality.

Introduction

Today the design and progression of ICs is only possible because of the development of a large number of computer-based tools. The steady exponential growth of the IC industry over many decades following Moore’s law would have been impossible without the extensive use of CAD technology. The progress of this design technology has been driven by the expanding scope and requirements of IC design, which started shortly after Robert Noyce invented the first silicon IC in 1959. The most important innovator in the early days of CAD technology for ICs is, without any doubt, Hermann K. Gummel, who passed away in 2022, the year of the 75th birthday of the bipolar transistor, which is particularly connected to his name. Today, nobody designs bipolar transistors without using a Gummel plot.

Therefore, it is the right time to honor Hermann K. Gummel’s fundamental contributions in several key domains of CAD technology. In this article six former coworkers of Hermann have joined forces to provide an overview of Hermann’s work and their personal views on his outstanding personality. The article is organized in four sections written by the different authors, highlighting different fields of CAD technology that have benefited most from Hermann’s significant contributions.

Numerical Device Modeling

The history of numerical modeling for semiconductor devices starts with Hermann’s landmark paper from 1964 [1], bearing the modest title “A Self-Consistent Iterative Scheme for One-Dimensional Steady State Transistor Calculations.” In this paper of 10 pages, which appeared in the October issue of IEEE Transactions on Electron Devices, he presented the nonlinear solution method that is still one of the most important algorithms within modern technology CAD (TCAD) models. Today it is typically addressed as Gummel’s nonlinear relaxation method or just Gummel’s method. One has to remember that, prior to 1964, computers had “core” memory sizes of a few thousand bytes and clock cycle times below 1 MHz, and would crash daily. Therefore, only algorithms that needed little memory on one hand and had a robust and fast convergence behavior on the other could be used. This is exactly what Hermann’s new algorithm offered for most applications. This algorithmic breakthrough, and the availability of accurate numerical solutions, created a boost for the art of bipolar transistor modeling in particular and for the numerical modeling of semiconductor devices in general, and it paved for the way to many important innovations in the years to come. Besides this key solution algorithm, Hermann’s paper from 1964 provides a wealth of additional information as most of his papers do. The most important details about the proper modeling of mobilities and recombination processes for silicon are included, and the typical alternatives for the formulation of boundary conditions are discussed as well. The possibility of computing small-signal parameters in a numerically stable manner is mentioned, and a method for including parasitic circuit elements is addressed. Moreover, a possible extension of the 1D model in [1], allowing the efficient modeling of the base crowding effect by coupling several 1D bipolar models in the base, is outlined. This idea was later realized by other groups (see, for example, [5]) and proved very useful for the further scaling of bipolar transistors. Finally, an efficient and simple method for modeling the self-heating of semiconductor devices, which is still used today, is described in [1].

The availability of the 1D numerical model allowed Hermann and his coworkers new insights into bipolar effects like high injection and base push-out [3], which were controversial issues at that time. Moreover, it allowed the investigation of complicated device operation like a silicon diode, backward biased in a strong impact ionization mode (a Read diode) and placed in a small resonant circuit environment allowing the generation of autonomous microwave oscillations. Hermann and his coworker Donald Scharfetter studied this device for several years as some lesser known publications show (e.g., [4]). Finally, they summarized their results in Hermann’s second landmark paper, “Large Signal Analysis of a Silicon Read Diode Oscillator,” which appeared in the January 1969 issue of IEEE Transactions on Electron Devices [2] and described the first transient numerical device simulation. This new method allowed the computation of the limit cycle of a microwave oscillator, exploiting the strong nonlinearity of impact ionization in silicon. The transient analysis is based on a semi-implicit time integration method that enhances the stability of time integration, but the key detail mentioned mostly in the context of this article is the Scharfetter–Gummel discretization method for the particle current densities between two grid nodes. This discretization formula is explicitly given in this article for the first time but probably already existed in a hidden manner in [1], where the same principles are used for the discretization of electron and hole particle current densities. This discretization method and/or generalizations of it are adopted in virtually every TCAD simulator in use today since it turned out to be very difficult to generate stable TCAD solutions on coarse grids without this method.

Hermann’s early paper [1] indicates that he was one of the most sophisticated scientific programmers of his time, and, amazingly, he managed to keep this skill level through the demanding times as lab director and well beyond his official retirement. Being on the forefront of the development of CAD for ICs for decades made him an ideal mentor for the younger engineers and scientists at Bell Labs and beyond. Discussing a technical problem with him was a career highlight and an unforgettable moment for everybody who was able to enjoy his deep and broad knowledge. Generations of young engineers and scientists considered it an honor to present their work when he was present. His feedback was typically very polite but firm when he detected weaknesses. One example is his doubt about the general validity of the Ward–Dutton charge-oriented model [6] for the low-frequency terminal current modeling of MOSFETs. His doubt triggered a fundamental research project, which he closely monitored, that is summarized in the Habilitation-Thesis of Heinz K. Dirks [7]. The answer is that the ansatz in [6] is a good approximation for symmetric MOSFETs but fails for nonsymmetric transistors. Hermann actively supported the CAD activities at many universities and was personally involved in making them successful.

Hermann’s language was always very precise, and he disliked overstatements. For example, he always used the term Chynoweth’s formula and refused to use the term Chynoweth’s law as most people do for the formula that describes impact ionization in most TCAD simulations. Even decades after his official retirement, Hermann seemed to always be online. E-mails were answered in perfect English within hours, and sometimes even minutes, and we could count on his support when we needed it.

Bernd Meinerzhagen and E. James Prendergast

Numerical Calculation of Multiterminal Resistances and Capacitances

In 1970, Hermann published a very efficient method for the calculation of multiterminal resistances and capacitances with irregular shapes in two dimensions [8]. The method is based on Cauchy’s integral formula, which states that “a holomorphic function defined on a disk is completely determined by its values on the boundary of the disk.” Hermann made ingenious use of this and developed a software tool called RESCAL. Its original purpose was to calculate resistances, but it turned out to be very useful as well for calculating capacitances in IC designs. However, in the original version of RESCAL there were some limitations on the shape of the boundary. Consequently, when he retired as lab director and continued working as a consultant for Bell Labs, Hermann had more time and wanted to expand the capabilities of RESCAL to more general cases. For this project, he was looking for someone to work with him, and one day a department head in Hermann’s former lab asked me if I would like to work with him. I told him that I had heard Hermann was a workaholic and a “slave driver,” so I was a bit hesitant. Then he suggested I have a one-on-one meeting to talk with Hermann. At the meeting, I asked Hermann bluntly about his reputation. He told me it was far from the truth. He would welcome people to work extra hours if they were interested enough in their work, but he had never required or even requested them to work overtime. Even when another director asked him to get his people to do extra work because that director’s group was behind schedule, Hermann told me he had flatly refused because it was their problem, and he was not going to ask his own people to make up for it. So, I decided to take up the offer to work with him on RESCAL. It became a very useful tool, and I applied it to numerous cases in the following years (see Figure 1 for a typical RESCAL simulation result). It turned out that the time I worked with Hermann was the best period in my career at Bell Labs. Hermann was a genius—well, a supergenius—but he was also a warm, kind gentleman. (Figure 2 shows Hermann at a meeting with some of the authors.)

Figure 1. Numerical solution of 2D Laplace’s equation within a star-shaped domain calculated by RESCAL. Constant Dirichlet boundary conditions are applied on the thick boundary lines, and homogeneous Neumann boundary conditions on the other parts of the boundary. Inside the star, dashed lines are field lines, and solid lines are equipotential lines.

Figure 2. Picture from the state of the lab meeting in 1987 with Hermann K. Gummel (second row, second from left), Ken Haruta (first row, far right), Bernd Meinerzhagen (third row, far left), Laurence W. Nagel (third row, second from right), and E. James Prendergast (second row, far left).

Ken Haruta

Compact Modeling

Hermann’s contributions to, and influence over, compact models (i.e., models that are used for circuit simulation for IC design) and how compact models should be formulated, tested, and verified loom large to this day.

Hermann’s first foray into compact modeling was in 1969 [9], on the depletion capacitance of pn-junction diodes. Standard theory predicts that, for a voltage V applied across a junction, the capacitance is ${C} = {C}_{0} / {(}{1}{-}{V} / {\phi}_{\text{bi}}{)}^{m}$, where ${C}_{0}$ is the capacitance at ${V} = {0}$, ${\phi}_{\text{bi}}$ is the built-in potential of the junction, and m is a coefficient of around 1/3 to 1/2. This form has an obvious numerical problem as V approaches ${\phi}_{\text{bi}}$ in forward bias: it blows up to infinity! This issue could be avoided when analysis was done by hand, but it was a big problem as circuit analysis programs became more widely used in the late 1960s and early 1970s. The first proposed solution to this problem was from Hermann [9]. Moreover, his approach gives physically correct behavior: C does not “blow up” but peaks as V approaches ${\phi}_{\text{bi}}$, and then decreases to zero for ${V}\,{≫}\,{\phi}_{\text{bi}}$, exactly as it should because the depletion charge (and hence the capacitance) disappears. Many modern formulations for depletion charge modeling are derivatives of this approach.

Hermann’s most far-reaching contributions in compact modeling, from 1970, were the formulation of the integral charge-control relation (ICCR) [10] and the application of that to a compact model for bipolar junction transistors (BJTs) in [11], which gives what is now called the Gummel–Poon, or GP, model. Shockley had developed the ideal diode model in the 1940s, which shows that the diode current depends exponentially on V, based on pioneering physical analysis detailed in his book [12]. Subsequent BJT models were predicated on that, and despite invoking some “physical” analyses, were based primarily on empirical ${\alpha} = {I}_{C} / {I}_{E}$ and ${\beta} = {I}_{C} / {I}_{B}$ parameters, where ${I}_{C}$, ${I}_{E}$, and ${I}_{B}$ are the collector, emitter, and base currents, respectively. As the use of BJTs expanded, and a more accurate and detailed understanding as well as the modeling of nonideal effects were needed, it was essentially impossible to “shoehorn” into these empirically based BJT models things like the Early effect (modulation of ${I}_{C}$ by the collector voltage ${V}_{C})$ and high-level injection (decrease in ${\beta}$ at a high base voltage ${V}_{B}{)}$.

Hermann’s ICCR and the GP model physically, naturally, and elegantly embody the fundamentals of how BJTs operate. They represent a revolution in the understanding of BJT behavior and of how a good compact model should be developed: based on physics, but with insight and intuition as to how to derive relatively simple, yet accurate, algebraic equations from complex partial differential equations. The GP model gives the collector–emitter (i.e., transport) current as \begin{align*}{I}_{\text{CE}} = & {A}_{E} \frac{{q}\,{\bullet}\,{n}_{i}^{2}\,{\bullet}\,{\phi}_{t}\,{\bullet}\,{\mu}}{\mathop{\int}\nolimits_{0}\nolimits^{{t}_{B}}{{N}_{B}(x)dx}} \\ & {\times}\,\frac{{\exp}{\left(\frac{{V}_{B}}{{\phi}_{t}}\right)}{-}{\exp}{\left(\frac{{V}_{C}}{{\phi}_{t}}\right)}}{{q}_{B}} \end{align*} where ${A}_{E}$ is the area of the emitter, q is the elementary charge, ${n}_{i}$ is the intrinsic carrier concentration, ${\phi}_{t}$ is the thermal voltage, ${\mu}$ is mobility, ${t}_{B}$ is the base thickness, ${N}_{B}{(x)}$ is the doping level in the base (which depends on position x in the base, from the emitter to the collector), and ${q}_{B}$ is the so-called normalized based charge (which has a value of one with no bias applied). The Early effect and modeling of high-level injection appear naturally in Hermann’s formulation through the bias dependence of ${q}_{B}$ (see [11] for details).

One of the most beautiful features of this model is that it captures, to first order, all important aspects of BJT behavior: the dependence on geometry (via ${A}_{E})$; the dependence on temperature (directly through ${\phi}_{t}$ and indirectly though ${n}_{i}$, which depends strongly on temperature, and ${\mu}$, which depends weakly on temperature); the dependence on the structural (and designable) parameters ${t}_{B}$ and ${N}_{B}$; the dependence on bias (directly, and through ${q}_{B})$; and, indirectly, statistical variations (through variations in ${A}_{E}$, ${t}_{B}$, and${N}_{B}$).

Hermann’s ICCR and the GP model are works of ingenuity and formed the basis of all of the more advanced BJT compact models developed since the ICCR and GP model were introduced, way back in 1970. In our opinion, they also form by far the best “mental” picture of how a BJT works; ${\alpha}$ and ${\beta}$ should have vanished into the mists of time but, alas, have not done so yet (more than 50 years since Hermann blazed the path to the future!).

Given the importance of the dopant sheet density in the base, ${\int}_{0}^{{t}_{B}}{N}_{B}{(x)}{dx}$ in the previous expression, this quantity is now referred to as the Gummel number (that name also covers variants that may include ${\phi}_{t}\,{\bullet}\,{\mu}$ and/or ${n}_{i}$, but it is the base thickness and doping profile that are key). Verification of a BJT model versus data is now universally done via a log-linear plot of ${I}_{C}$ and ${I}_{B}$ versus ${V}_{B}$, which is called the Gummel plot [13].

As CMOS technology became dominant, the need for accurate MOS transistor models escalated. Multiple approaches were investigated, and many of these worked well enough for digital applications but had significant shortcomings for analog and RF applications. Complaints about, and benchmarks to test, capabilities of MOS transistor models from the perspective of circuit designers were voiced in [14] and [15]. However, it was not obvious how to translate some design requirements into “physical” benchmarks that model developers could understand.

The common perception that the MOS transistor drain current ${I}_{D}$ varies exponentially with gate bias ${V}_{G}$ in weak inversion (“subthreshold”) is incorrect—the deviation from exact exponential variation is critical for the design of modern low-power circuits, yet “threshold voltage”-based MOS transistor models completely missed this. How do you test if a model captures this physical behavior?

In strong inversion (high ${V}_{G})$, at low drain bias, ${I}_{D}$ varies approximately linearly with drain voltage ${V}_{D}$. In weak inversion (low ${V}_{G}$), ${I}_{D}$ varies as ${1}{-}{\exp}{(}{-}{V}_{D} / {\phi}_{t}{)}$. How do you test if a model correctly captures this behavior and transitions smoothly from low to high ${V}_{G}$?

The source and drain of most MOS transistors are symmetric. How do you determine if a MOS transistor model (which has four terminals) is properly symmetric? (This is critical for modeling the behavior of some specific RF CMOS circuits.)

Hermann’s knowledge of devices and models led him to develop benchmark tests for each of these three behaviors (see [16], where the tests developed by Hermann were first presented outside Bell Labs). They are known as the Gummel tree-top test, the Gummel slope ratio test, and the Gummel symmetry test, respectively. All modern MOS transistor models are now required to pass those tests.

There are other hidden gems in Hermann’s work that are often overlooked (which is why it is important to read everything in all of his papers carefully).

First, many people have “discovered” that a plot of ${\log}{(}{I}_{C}{)}$ versus ${V}_{B}$ is not exactly a straight line with slope ${1} / {\phi}_{t}$, as the preceding GP equation looks like it predicts. They therefore “improve” the model by replacing ${\phi}_{t}$ with ${n}\,{\bullet}\,{\phi}_{t}$, where n is some “ideality” coefficient that can be different from 1. There are reasons to include such a coefficient, especially for heterojunction bipolar transistors because some (second-order) physics is omitted in the derivation of the ICCR and the GP model. However, by far the most common reasons for deviation from the simple theory predictions are that the measurement temperature is not controlled accurately, and that the reverse Early effect (“emitter capacitance”) is not taken into account (which it is in the GP model). Both of these are explicitly pointed out in [11] but are still widely overlooked.

Second, the “classic” view of ${f}_{T}$ from the 1950s, yet still in widespread use today, is that it is “the frequency where the small signal version of ${\beta} = {1}$.” This definition has many shortcomings. Hermann’s little-known article [17] is the key bridge between the classic and modern views of what ${f}_{T}$ is.

Shiuh-Wuu Lee and Colin McAndrew

Electronic Design Automation

I first met Hermann in 1973 when I was interviewing for a job at Bell Laboratories. At that time, Hermann already had pioneered the use of what we now call TCAD tools to understand the operation of the BJT, he had derived the integral charge relation for the BJT, and with Sam Poon he had published the Gummel–Poon model for circuit simulators. In fact, I had implemented the Gummel–Poon model in Spice at that point, and I had developed an enormous respect for the elegance of the integral charge relation. When I interviewed Hermann, I was amazed at how quiet and shy he was, and I found myself wondering how somebody so brilliant and so successful could be so humble.

For most engineers, Hermann’s work with BJTs would be sufficient for a distinguished career with the accolades that accompany such accomplishments. But Hermann was just getting started. At this point, Hermann was a second-level manager responsible for a department of 30 engineers, but he still made time for engineering breakthroughs. Hermann’s department was part of a laboratory that was using polycells and CAD tools to develop custom MOS ICs for the Bell System. While polycells were very successful in rapid prototyping of custom ICs, our department was facing some real design issues. The circuits that were developed were too large to be simulated by ADVICE, the Bell Labs version of Spice that I had developed. But the Bell Labs logic simulator, called LAMP, which could easily accommodate the size of the circuits, was not accurate enough to detect the timing errors that were plaguing the MOS circuits.

In the early 1970s, Hermann conceived the idea of a timing simulator that would run much faster and accommodate much larger circuits, compared to ADVICE, yet provide sufficient accuracy for MOS circuits. I remember Hermann calling me at the IEEE International Solid-State Circuits Conference to tell me that he was thrilled that he couldn’t sleep that night because he came up with an idea for a faster simulator and he wanted to run it past me. I was amazed at the idea and enthusiastically encouraged Hermann to pursue it.

Hermann’s work resulted in the prototype program MOTIS (MOS Timing Simulator) [18], which was the beginning of “fast Spice” timing simulators—more accurate than logic simulators and much faster than circuit simulators. Hermann combined the computational techniques of table lookup models, implicit integration, and a direct solution technique to accomplish this task. To quote A. Richard Newton, Dean of the UC Berkeley College of Engineering, “While I think Hermann would agree with me that none of the specific mathematical techniques used in MOTIS was new in and of itself, it was the combination of techniques, data structures, and code that produced a simulation system that had a very broad impact. Once the work was published, it was implemented and extended in virtually every major semiconductor house and at many universities throughout the world. I was personally involved in the development of one such version, MOTIS-C at Berkeley, and so I can personally attest to both the elegance and the engineering insight Hermann gave us all in that work.” [19].

Hermann had an uncanny intuition about the design problems that the ever-increasing size of ICs—fueled by Moore’s law—were impressing on CAD tools. Hermann realized long before many experts in the IC business that computers were the only way to address complex circuit design problems, just as he had realized that computers were the only way to address semiconductor physics problems 20 years earlier.

One example of a CAD tool that Hermann pioneered was his SCHEMA program, which allowed a designer to enter a circuit description graphically by entering a schematic of the circuit. At the time SCHEMA was developed, the traditional manner of entering a circuit description was a textual “netlist” file that was easily understood by a simulator but very error prone and painful for a designer. Hermann would sit for hours with designers observing how they entered netlists for simulation, which led him to understand that a schematic entry tool would save designers an enormous amount of time.

Hermann also built a very successful graphical editor, called GRED, and this also illustrates how he first came to understand the human interface before developing a CAD tool. I personally witnessed Hermann sitting beside designers for hours on end, watching how they did their work, how they implemented commands, and observing the number of keystrokes needed, all the while taking notes and thinking about ways to improve their efficiency. He then developed GRED from the notes he had gathered.

Hermann was also the first to build and publish a practical device extraction tool. His HCAP program [20] allowed a designer to extract a netlist from the physical layout of an IC. Before HCAP, designers used colored pencils and a Calcomp plot of the layout to check that the layout was indeed the circuit the designer intended.

Hermann was a true visionary and had a clear understanding that the size and complexity of ICs was increasing much faster than a human’s ability to cope. CAD tools were now a necessary part of the IC design process, and Hermann was at the forefront of electronic design automation tool development, while managing a department that had now grown to more than 100 engineers at two Bell Labs locations.

Laurence W. Nagel

Conclusion

When Hermann K. Gummel passed away, we lost one of the key founding fathers of IC industry. He was an outstanding scientist, a great lab manager and leader, and a most admired individual and mentor, all at the same time. He led by example, an example we all had difficulty keeping up with, but one that certainly shaped our own approach toward science and management. He remains the inspiration for all of us.

Biographies

Ken Haruta (haruta@alum.mit.edu) , retired, was with Bell Labs, Allentown, PA 18103 USA.

Shiuh-Wuu Lee (shiuhwuu.lee@gmail.com) resides in Saratoga, California, US 95070 USA.

Colin McAndrew (mcandrew@ieee.org) is with NXP Semiconductors, Chandler, AZ 85224 USA.

Bernd Meinerzhagen (b.meinerzhagen@tu-bs.de) is with Technische Universität Braunschweig, Fakultät für Elektrotechnik, Informationstechnik, Physik, 38106 Braunschweig, Germany.

Laurence W. Nagel (lwn@omega-enterprises.net) is with Omega Enterprises Consulting, Kensington, CA 94708 USA.

E. James Prendergast (jim@prenkin.com) resides in Durango, CO 81301 USA.

References

[1] H. K. Gummel, “A self-consistent iterative scheme for one-dimensional steady state transistor calculations,” IEEE Trans. Electron Devices, vol. ED-11, no. 10, pp. 455–465, Oct. 1964, doi: 10.1109/T-ED.1964.15364.

[2] D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a silicon read diode oscillator,” IEEE Trans. Electron Devices, vol. ED-16, no. 1, pp. 64–77, Jan. 1969, doi: 10.1109/T-ED.1969.16566.

[3] H. C. Poon, H. K. Gummel, and D. L. Scharfetter, “High-injection in a bipolar transistor,” IEEE Trans. Electron Devices, vol. ED-16, no. 5, pp. 455–457, May 1969, doi: 10.1109/T-ED.1969.16777.

[4] H. K. Gummel and D. L. Scharfetter, “Avalanche region of IMPATT diodes,” Bell Syst. Tech. J., vol. 45, no. 10, pp. 1797–1827, Dec. 1966, doi: 10.1002/j.1538-7305.1966.tb02436.x.

[5] W. L. Engl and H. K. Dirks, “Functional device simulation by merging numerical building blocks,” in Numerical Analysis of Semiconductor Devices and Integrated Circuits, B. T. Brown and J. J. H. Miller Eds. Dublin, Ireland: Boole Press, 1981, pp. 34–62.

[6] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS-transistor capacitances,” IEEE J. Solid-State Circuits, vol. SSC-13, no. 5, pp. 703–708, Oct. 1978, doi: 10.1109/JSSC.1978.1051123.

[7] H. K. Dirks, “Kapazitätskoeffizienten nichtlinearer dissipativer systeme,” Habilitation thesis, RWTH Aachen University, Aachen, Germany, 1988.

[8] B. R. Chawla and H. K. Gummel, “A boundary technique for calculation of distributed resistance,” IEEE Trans. Electron Devices, vol. ED-17, no. 10, pp. 915–925, Oct. 1970, doi: 10.1109/T-ED.1970.17095.

[9] H. C. Poon and H. K. Gummel, “Modeling of emitter capacitance,” Proc. IEEE, vol. 57, no. 12, pp. 2181–2182, Dec. 1969, doi: 10.1109/PROC.1969.7529.

[10] H. K. Gummel, “A charge control relation for bipolar transistors,” Bell Syst. Tech. J., vol. 49, no. 1, pp. 115–120, May 1970, doi: 10.1002/j.1538-7305.1970.tb01759.x.

[11] H. K. Gummel and H. C. Poon, “An integral charge control model of bipolar transistors,” Bell Syst. Tech. J., vol. 49, no. 5, pp. 827–852, May 1970, doi: 10.1002/j.1538-7305.1970.tb01803.x.

[12] W. Shockley, Electrons and Holes in Semiconductors. Princeton, NJ, USA: Van Nostrand, 1950.

[13] “Gummel plot.” Wikipedia. Accessed: Feb. 1, 2023. [Online] . Available: https://en.wikipedia.org/wiki/Gummel_plot

[14] Y. Tsividis, “Problems with precision modeling of analog MOS LSI,” in Proc. Int. Electron Devices Meeting, 1982, pp. 274–277, doi: 10.1109/IEDM.1982.190272.

[15] Y. Tsividis and K. Suyama, “MOSFET modeling for analog circuit CAD: Problems and prospects,” IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 210–216, Mar. 1994, doi: 10.1109/4.278342.

[16] C. McAndrew, H. K. Gummel, and K. Singhal, “Benchmarks for compact MOSFET models,” in Proc. Sematech Workshop Compact Models, 1995.

[17] H. K. Gummel, “On the definition of the cutoff frequency fT,” Proc. IEEE, vol. 57, no. 12, pp. 2159–2159, Dec. 1969, doi: 10.1109/PROC.1969.7509.

[18] B. R. Chawla, H. K. Gummel, and P. Kozak, “MOTIS – An MOS timing simulator,” IEEE Trans. Circuits Syst., vol. CAS-22, no. 12, pp. 901–910, Dec. 1975, doi: 10.1109/TCS.1975.1084003.

[19] A. R. Newton, Presentation of the 1994 Phil Kaufman Award to Dr. Hermann K. Gummel, Nov. 1994. [Online] . Available: https://people.eecs.berkeley.edu/∼newton/Presentations/Kaufman/HKGPresent.html

[20] P. A. Swartz, B. R. Chawla, T. R. Luczejko, K. Mednick, and H. K. Gummel, “HCAP – A topological analysis program for IC mask artwork,” in Proc. IEEE Int. Conf. Comput. Des., Port Chester, NY, USA, Oct./Nov. 1983, pp. 298–301.

Digital Object Identifier 10.1109/MED.2023.3262750

Development of Modern Bipolar Transistors: A Personal Journey and Perspective

Tak H. Ning

©SHUTTERSTOCK.COM/POCKETHIFI

The point-contact transistor was invented in 1947 by Bardeen and Brattain [1], and the sandwich-like BJT was invented by Shockley in 1948 [2]. While point-contact transistors were made and used briefly for a few years, it is Shockley’s sandwich-like device structure that is commonly referred to as a bipolar transistor.

The development of bipolar transistors in the early 1950s was to replace the vacuum tubes in data processing systems. At the beginning, transistors were used to replace vacuum tubes not for lower cost but for a much lower system failure rate, lower power dissipation, and a smaller system form factor.

Silicon Bipolar Technology Prior to the Mid-1970s

Bipolar Transistor Device Structures

At IBM, the development of bipolar transistor technology progressed rapidly in the mid-1950s, driven by the computer project named STRETCH [3]. Figure 1 shows schematically two of the advanced bipolar transistors developed at IBM for the company’s early computer systems [3]. To fabricate a transistor, we start with a lightly doped P-type substrate wafer. An n⁺ subcollector region is then formed in the P-type substrate by arsenic diffusion or by implantation followed by diffusion. A lightly doped n-type epitaxial layer is then grown. The thickness of the epitaxial layer is determined by the desired minimum separation between the bottom of the P-type intrinsic base region and the top of the n⁺ subcollector. Each transistor is isolated laterally by heavily doped P-type pockets and the P-type wafer substrate. The P-type base region is formed by boron diffusion or by boron implantation followed by diffusion. The subcollector layer is there to reduce collector resistance.

Figure 1. Bipolar transistors developed at IBM for use in its computer systems. (a) An earlier transistor structure without a recessed field oxide. (b) A more advanced transistor with a recessed field oxide, which was formed by masked thermal oxidation of recessed silicon regions.

The base width ${W}_{B}$ of a bipolar transistor is given by \[{W}_{B} = {x}_{jB}{-}{x}_{jE} \tag{1} \] where ${x}_{jB}$ is the base junction depth [measured from the silicon (Si) surface to the bottom of the P-type base region] and ${x}_{jE}$ is the emitter junction depth (measured from the Si surface to the bottom of the n⁺ emitter region). It is clear from (1) that ${x}_{jE}$ should be comparable to or smaller than ${W}_{B}$ to achieve transistors with controlled and reproducible thin base widths. Thus, one direction in the development of bipolar process technology in the early days was to reduce the emitter junction depth. By 1966, emitter junction depths as shallow as ${7}\,{\mu}{\text{ in}}$ ${(}{0.18}\,{\mu}{\text{m}}{)}$ were demonstrated at IBM [4].

Bipolar Logic Circuits

Since the invention of the bipolar transistor, many bipolar logic circuits, e.g., DTL, TTL, ECL, merged-transistor logic (MTL), and integrated injection logic (I2L), have been used in products. Here, only ECL and MTL/I2L are briefly discussed.

Figure 2 presents a typical ECL circuit. It was invented by Yourke, in 1956 [5], and first used in IBM 7090 systems, announced in 1958. The transistor ${Q}_{4}$sets the switch current ${I}_{S}$. When the input ${V}_{\text{in}}$ turns on ${Q}_{1}$, ${I}_{S}$ flows through ${Q}_{1}$ and the load resistor ${R}_{L}$ connected to ${Q}_{1}$. When the input ${V}_{\text{in}}$ turns off ${Q}_{1}$, ${I}_{S}$ is switched from passing through ${Q}_{1}$ and its load resistor to passing through ${Q}_{2}$ and its load resistor. There is little transient current, and, hence, little switch noise, seen at the metal line connected to ${V}_{\text{CC}}$. The logic swing for an ECL circuit can be rather small, typically about 400 mV. ECL circuits were, and still are, the fastest logic circuits.

Figure 2. An ECL gate with fan-in = fan-out = 1 and an output capacitance loading of C_L. Both the inverting and the noninverting outputs are shown.

In 1972, an exciting bipolar logic circuit was announced by Hart and Slob, of Philips [6], and Berger and Wiedmann, of IBM [7]. Hart and Slob called their circuit I2L, and Berger and Wiedmann called their circuit MTL. Figure 3 is a schematic of an I2L/MTL logic gate. It is by far the densest logic circuit. It uses minimum-size devices and requires one p-n-p per gate for current injection and one n-p-n per fan-out. Thus, the inverter in Figure 3 requires only four transistors. The same physical I2L/MTL can be operated at different injection currents, resulting in different circuit speeds, simply by varying the base–emitter bias voltage of the p-n-p ${V}_{\text{CC}}$ in Figure 3. In the 1970s, CMOS was still in its infancy. Thus, the advent of I2L/MTL generated a lot of excitement in the semiconductor industry. Many companies rushed into developing LSI chips using I2L/MTL.

Figure 3. An I2L/MTL gate with three fan-outs. Here, CL represents the load capacitance at the fan-out collector C1. When built using vertical transistor processes, the n-p-n transistors operate upside down, with the top n-regions acting as collectors and the bottom connected n-regions as a common emitter.

Bipolar Technology Circa 1977

As ${x}_{jE}$ is reduced to achieve a small ${W}_{B}$, the base current increases because more and more holes can reach the metal emitter contact before recombining. As the base current increases, the base doping concentration is often reduced to maintain adequate current gain. A computer simulation study published in 1979 by Gaur [8] showed that the intrinsic base sheet resistance of a transistor having ${x}_{jE} = {30}\,{\text{nm}}$ increased to almost ${130}{k}{\Omega} / {□}$, causing the ${f}_{\max}$ of the transistor to drop to 6 GHz. The net is that the transistors in Figure 1 are not scalable.

By 1977, partly due to the recognition that bipolar transistors, as represented in Figure 1, were not scalable to thinner bases for better performance and partly due to the excitement generated by MOSFET and CMOS advances, research activities on Si bipolar technology, particularly in the United States, had fallen off drastically, as evidenced by a lack of publications on the subject. Of the 281 papers published in IEEE Transactions on Electron Devices in the 12 months between September 1976 and August 1977, only 19 were on Si bipolar. Of the 19 Si bipolar papers, only five were by U.S. authors. Major universities and research laboratories in the United States either never had research programs on Si bipolar to begin with or had phased them out by then.

Nonetheless, research activities on novel bipolar technology were active in Japan and Europe, mostly related to using heavily doped poly-Si as the doping source for forming and contacting the emitter and to using doped poly-Si to form resistors [7], [8], [9], [10], [11], [12], [13]. Figure 4 illustrates perhaps the most advanced bipolar device structure reported by February 1977. It uses arsenic-doped poly-Si as a diffusion source to form the emitter and contact the collector, and it uses the overhang in the poly-Si edge to shadow metal evaporation, achieving the self-alignment of the base contact to the emitter [13].

Figure 4. A bipolar transistor built using the so-called elevated electrode IC technology, reported at the 1977 International Solid-State Circuits Conference.

Development of Modern Si Bipolar Transistors Since 1977

From the late 1950s to the mid-1990s, Si bipolar was the backbone technology for IBM’s data processing and computing systems. IBM had strong R&D programs on bipolar technology and circuits in its product development laboratories. In 1976, upper management decided that the IBM Research Division should establish a program on Si bipolar technology, with an objective of looking ahead and exploring the white space in bipolar technology not covered by the development laboratories. In January 1977, an exploratory bipolar devices and circuits group was formed at the IBM T.J. Watson Research Center; thus began the exciting years of Si bipolar technology exploration there. When the group was first formed, in January 1977, it consisted of six members: H.N. Yu was acting manager of the group, D.D. Tang focused on device design and modeling, P.M. Solomon focused on circuit design and modeling, T.H. Ning focused on device technology, G. Feth focused on circuit applications, and M.G. Smith focused on system applications. About a year later, R.D. Isaac, who had just obtained his Ph.D. degree from the University of Illinois Urbana-Champaign, joined the team and focused on process technology development. A bit later, S.K. Wiedmann, from IBM Boeblingen Laboratories, joined the team to focus on using the newly developed bipolar technology for logic and memory applications. Some of the key research directions taken by the team, and others at IBM, are described in the following.

Density Improvement and Capacitance Reduction Using Self-Alignment Schemes

FIGURE 5. The self-aligned bipolar transistor, using poly-Si for the base contact and self-aligning the emitter opening to the base poly-Si layer, reported at the 1980 International Electron Devices Meeting. (a) After patterning the base poly-Si layer and the initial emitter opening. The poly-Si is etched by a combination of RIE and preferential wet etching. (b) After depositing a conformal oxide layer, followed by thermal drive in to form the extrinsic base regions. (c) After etching the deposited oxide by RIE to form an oxide spacer on the vertical surface of the base poly-Si layer, and then forming the intrinsic base and the emitter by ion implantation.

It is evident from the device schematics in Figures 1 and 4 that the intrinsic device area of a vertical bipolar transistor, defined by the emitter area, is very small compared to the total area occupied by the transistor, which includes the areas occupied by contacts and isolation. A large parasitic device area also means large parasitic device and wire capacitances.

The transistor in Figure 4, with its metal base contact self-aligned to an emitter formed by diffusion from a doped poly-Si layer, has a significantly smaller total device area than the transistors in Figure 1. However, in our view, the fabrication process makes it difficult to optimize the doping profile of the intrinsic base and collector regions (the base and collector regions directly underneath the emitter opening). As a result, we decided to pursue the idea of first using boron-doped poly-Si to form the base contact and then self-align the emitter opening to the base poly-Si layer. By 1977, reactive ion etching (RIE) was already widely used in advanced technology development at IBM [14], [15]. We decided to use RIE to form an oxide spacer on the vertical etched surface of the base poly-Si to define the emitter opening. In this scheme, the intrinsic base and collector regions can be readily optimized by ion implantation through the emitter opening. The result is the self-aligned transistor in Figure 5, first reported at the 1980 International Electron Devices Meeting (IEDM) [16].

The IBM team did explore a self-alignment scheme similar to that in Figure 4. Indeed, for applications where the intrinsic device profile is not critical for circuit speed, it is a good alternative. The self-alignment scheme was employed to demonstrate the high-density and high-speed I2L/MTL circuit, described schematically in Figure 6, at the 1979 IEDM [17]. Using ${2.5}{-} {\mu}{\text{m}}$ design rules, an I2L/MTL gate with a fan-out of three showed delays as small as 0.8 ns [18].

Figure 6. Self-aligned I2L/MTL circuits using metal base contacts self-aligned to the emitter. The emitter was formed by diffusion from a heavily doped poly-Si layer (the dark layer in the drawing). The metal contact to the base is separated from the emitter by an oxide sidewall spacer [17], [18]. (a) The cross-sectional schematic of the device structure, for a circuit with three fan-outs. (b) The corresponding circuit schematic.

Density Improvement and Capacitance Reduction Using Deep Trench Isolation

It is obvious from the schematics in Figures 1 and 4 that the junction isolation scheme, i.e., the large and deep vertical p-pockets, takes up a lot of area and has correspondingly large collector–substrate capacitance. The concept of using deep trench isolation to replace p-pocket isolation was evolving at the time at IBM [19], [20], so we decided to pursue deep trench isolation.

Dependence of Current Gain on Emitter Contact and Poly-Si Emitter

At IBM, the poly-Si emitter was discovered unexpectedly. A series of experiments, illustrated in Figure 7, was designed to study the differences among implanted and diffused shallow emitters contacted by silicide, aluminum, and arsenic-doped poly-Si. To avoid any ambiguity, all three kinds of emitter contacts were designed to be on the same wafers. The masking procedure was such that one of the devices [the device in Figure 7(b)] received no emitter implant at all but had the n⁺ poly-Si layer formed directly on the P-type base layer. There was no “diffusion from the doped poly-Si” thermal cycle. This device was not expected to work since the conventional wisdom at the time suggested that the poly-Si contact would behave like an ohmic contact, due to recombination at the interface of the arsenic-doped poly-Si and the P-type single-crystal Si. However, we found, to our great surprise, that the device not only worked properly but also showed the largest current gain of the four devices (see Table 1). We published the data from the planned experiments [21], [22] but kept the poly-Si emitter data proprietary.

Figure 7. (a) The emitter contact experiments in which (b) the poly-Si emitter was discovered.

Table 1. The typical measured current gains of the bipolar transistors sketched in Figure 7, for a base sheet resistance value of about 7 KΩ/4.

The physics and technology of the poly-Si emitter was the subject of intense studies in universities and industrial laboratories worldwide in the 1980s. Most of the papers up to 1989 were collected in one publication [23]. It is a good reference and contains an excellent introduction to the theoretical and experimental aspects of poly-Si emitter bipolar transistors.

Bipolar Transistor Design, Scaling, and Pedestal Collector

In operation, the speed of a vertical bipolar transistor increases with the collector current, reaching a peak, and then falls off rapidly as the collector current is increased further. The falloff of the speed at high collector currents is due to base widening, or the Kirk effect [24]. It occurs when the n-type collector doping concentration is not high enough to support the electron current emitted from the emitter and arriving at the collector. In other words, the maximum speed of a vertical bipolar transistor is not determined by its base width but by its collector doping concentration. This important point is central to a new procedure for optimizing the design of the intrinsic base and collector of a bipolar transistor in 1979 [25]. A theory for scaling this optimally designed transistor to smaller dimensions was also published the same year [26]. Several constraints and requirements are imposed in scaling the transistor. These constraints and requirements for ECL circuits are listed in Table 2. Here, ${V}$ is the power supply voltage, ${\Delta}{V}$ is the logic swing, ${C}_{\text{DE}}$ is the emitter diffusion capacitance, and ${C}_{\text{dBC}}$ is the base collector junction depletion layer capacitance. The power supply voltage remains constant in bipolar scaling because the turn-on voltage of a p-n diode is relatively independent of its area. Reducing the diode area by ${10}\,{\times}$ increases its turn-on voltage by only 60 mV. By following these constraints and requirements, the scaling theory suggests that the delay of an ECL circuit is reduced by ${\alpha}$ when the emitter area is reduced by ${\alpha}^{2}$ and the circuit switch current density is increased by ${1} / {\alpha}^{2}$. That is, an ECL circuit implemented in an optimally designed bipolar technology scales with speed improvement but without a reduction in power dissipation. In other words, just two years after the start of the bipolar research program, the IBM team knew that power dissipation issues would eventually limit the scaling of ECL circuits.

Table 2. The constraints and requirements in ECL scaling [26].

The device design methodology and scaling theory serve as a valuable guide for designing the intrinsic base and collector regions. To tailor the collector doping concentration directly under the emitter only, the pedestal collector concept [27] was used. For our self-aligned transistor structure (see Figure 5), the pedestal collector was formed by high-energy ion implantation when the emitter opening was defined. In the literature, this implanted pedestal collector is often referred to as a self-aligned implanted collector.

Trench-Isolated Self-Aligned Bipolar Transistor Having Poly-Si Emitter and Pedestal Collector

By 1977, driven by a ${1}{-} {\mu}{\text{m}}$ n-channel MOSFET VLSI research program, electron beam lithography was available at IBM Research [28]. So, we decided to pursue integration of the self-aligned bipolar transistor, shown in Figure 5, and deep trench isolation with a recessed field oxide, using ${1.25}{\kern0.0em-} {\mu}{\text{m}}$ electron beam lithography. The final device structure is displayed schematically in Figure 8. The first successful experiment, showing ECL gates with a delay of 114 ps at a power dissipation of 4.9 mW, was reported at the 1982 International Solid-State Circuits Conference [29]. At the time, we decided to keep the details of the poly-Si emitter and the pedestal collector proprietary and, hence, did not highlight them in publications.

Figure 8. A deep trench-isolated double-poly-Si self-aligned n-p-n transistor with a pedestal collector.

In the 1980s, many research papers on using poly-Si to form self-aligned bipolar transistors with a small base–collector junction area were published. Among them, the sidewall base contact structure [30] and the superself-aligned transistor structure [31] have the potential of a smaller base–collector junction area than the structure in Figure 8.

SiGe Base Bipolar Transistors

At IBM Research, the first successful SiGe base transistor was reported, in 1987, using a molecular beam epitaxy process to form the SiGe layer [32]. A bit later, after Meyerson demonstrated an ultrahigh-vacuum–CVD process for forming SiGe layers with controlled Ge distribution [33], researchers at IBM started to explore replacing the implanted Si base with an in situ doped SiGe base formed by the new CVD process. They reported the successful integration of a poly-Si emitter with a graded-Ge SiGe base formed by the new CVD process in 1989 [34], [35].

Compared to Si base transistors, graded-Ge SiGe base transistors offer greatly improved device characteristics for RF and analog applications. Figure 9 is a plot of the relative improvement in current gain, Early voltage, and base transit time for a linearly graded SiGe base transistor compared to an Si base transistor of the same base doping profile, plotted as a function of the maximum bandgap lowering at the collector end. It shows a graded-Ge SiGe base transistor is much superior to an Si base transistor by these comparisons.

Figure 9. Relative improvements of a linearly graded-Ge SiGe base transistor compared to an Si base transistor.

Symmetric Lateral Bipolar Transistors on SOI

The bipolar transistors we have discussed so far are vertical transistors, where the collector current flow is vertical, i.e., perpendicular to the Si surface. From the early 1990s to the early 2010s, IBM had an SOI CMOS program. As the CMOS gate length was scaled down to about 50 nm, we adapted the SOI CMOS process to make thin-base complementary symmetric lateral bipolar transistors where the collector current flow is lateral, i.e., parallel to the Si surface. The integration of lateral n-p-n and p-n-p transistors on the same chip, as detailed schematically in Figure 10, was first reported at the 2011 IEDM [36]. Unlike a vertical transistor, a symmetric lateral transistor does not have the Kirk effect (the base widening into the collector). As a result, a symmetric lateral transistor can be operated at much higher current densities than a vertical transistor, without performance degradation.

Figure 10. The integration of n-p-n and p-n-p symmetric lateral bipolar transistors on SOI.

A Personal Perspective

The advent of the poly-Si emitter, together with the self-alignment and deep trench isolation schemes, enabled vertical bipolar transistors to achieve ultrathin base widths and reduced the device area and capacitance to values consistent with the fabrication processes employed. The pedestal collector scheme enabled the transistor collector to be optimized to its intended circuit application. In 1990, IBM announced a family of computer systems, the ES/9000 mainframe series, built using this advanced bipolar transistor together with four planarized metal layers. Figure 11 is a schematic of this bipolar technology [37].

Figure 11. The bipolar transistor and metallization used in IBM’s ES/9000 systems.

CMOS Conquering the Digital World and Reaching Its Speed Limit

The IBM ES/9000 was the most powerful family of mainframes ever produced using bipolar technology, but it was also the last generation of mainframes produced using bipolar technology. IBM switched from bipolar to CMOS for its S/390 (G3) processor in 1996, and Intel switched to all CMOS for its Pentium processors in the mid-1990s.

Many talks have been presented and papers written about why CMOS has replaced bipolar as the backbone of high-performance computer systems. In my opinion, the fundamental reason has to do with the fact that a CMOS circuit has negligible standby power dissipation, while a bipolar ECL circuit dissipates the same power in standby and during switching, as explained in the “Bipolar Transistor Design, Scaling, and Pedestal Collector” section. Thus, a digital system designer can put lots of “standby” CMOS circuits on a chip and in the system, with little additional cost associated with the chip and system cooling. The same design option is simply not available for systems built using vertical bipolar circuits.

However, every technology has its limits, and CMOS is no exception. For a long time, a common practice in designing a scaled CMOS device was to allow its off current to increase from one generation to the next, by reducing the device threshold voltage, to increase its on current to achieve the targeted performance of the scaled device. CMOS for high-performance computing started its march toward the scaling wall when its off current was capped at ${100}{\text{ nA}} / {\mu}{\text{m}}$, beginning with the 65-nm node. Capping the off current in designing scaled CMOS devices severely limits the speed (clock frequency) of microprocessors. Today, the maximum speed of high-performance CMOS microprocessors is about 5 GHz [38], practically the same as those in 2009.

Status of Bipolar and Some Thoughts on Its Future

SiGe base vertical bipolar transistors missed the “bipolar for high-performance computing” era completely but arrived just in time for the takeoff of the “personal wireless communication era.” As indicated in Figure 9, vertical SiGe base bipolar transistors are far superior than vertical Si base bipolar transistors in terms of current gain, Early voltage, and base transit time. SiGe base bipolar has been used in Wi-Fi power amplifiers for more than 10 years. Today, BiCMOS based on the integration of SiGe base bipolar and CMOS, with an ${f}_{\max}$ of 400 GHz, is finding increasing applications in optical and wireless networks, satellite communications, and infrastructures.

The doping concentration of the pedestal collector region of a vertical bipolar transistor (see Figure 8) is significantly lower than the base doping concentration. As a result, the maximum speed of a vertical bipolar transistor, including the SiGe base bipolar transistor, is limited by the Kirk effect, which sets in when the transistor collector current density is larger than can be supported by the collector doping concentration. When the Kirk effect becomes significant, the speed of a vertical transistor decreases, instead of increasing, as the collector current is increased further. Therefore, it will be a challenge to increase the ${f}_{\max}$ of vertical SiGe base bipolar transistors toward 1 THz.

Going forward, the symmetric lateral transistors on SOI (see Figure 10) offer intriguing opportunities. Compared to CMOS, they have a much higher drive current per unit “channel width” [39], and they do not have the Kirk effect. Computer simulations suggest that a lateral transistor could have an ${f}_{\max}$ of 1 THz or larger when operated at high collector currents [40]. And, with emitter/collector symmetry, lateral transistors have the same speed with emitter–base switching and with collector–base switching. ECL gates and I2L/MTL gates implemented in symmetrical lateral transistors should have comparable minimum gate delays. One can imagine designing a processor chip containing many identical cores in symmetric lateral bipolar technology, using I2L/MTL circuits and CMOS-like complementary bipolar circuits, with most cores running at a base speed in ultralow-power mode, some cores running at 10 to ${100}\,{\times}$ the base speed and dissipating 10 to ${100}\,{\times}$ higher power per core, and a couple of cores operating as accelerators running at ${1,000}\,{\times}$ the speed and dissipating ${1,000}\,{\times}$ the power of the ultralow-power cores [40], [41]. Such a “performance-on-demand” system design concept is beyond the reach of CMOS. However, just like any new device technology, it will take one or more compelling applications and a sound business case to drive the investments needed to take symmetric lateral bipolar transistors on SOI from concept and feasibility to volume manufacturing.

Biography

Tak H. Ning (tak.h.ning1@gmail.com) is a retired IBM fellow and a Life Fellow of IEEE.

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Digital Object Identifier 10.1109/MED.2023.3257127

Date of current version: 28 June 2023

My LSI Development Experience at Toshiba (1973–1999): Hard Working, Exciting, and Splendid Days

Hiroshi Iwai

©SHUTTERSTOCK.COM/METAMORWORKS

The LSI technology evolution from the 6-µm NMOS to the recent nano-CMOS is described based on my experience at Toshiba from 1973 to 1999. Unexpected problems often occurred, resulting in severe yield degradation and delays in development schedules. However, the severe problems and competitions among the strong rival companies have been the source of innovations and evolutions, having contributed to the realization of the super-intelligent society.

Introduction

The year 2025 will be the 100th anniversary of the invention of the Field-Effect Transistor (FET), by J.E. Lilienfeld [1]. At that time, probably no one, including him, could imagine the evolution of the FET idea to the recent nano-CMOS VLSI circuits—a typical nanoelectronic device today—that has opened up the super-intelligent human society in the 21st century. Figure 1 shows a brief history of transistor/LSI development. Device miniaturization has been continuously accomplished in the 50 years since the first-generation LSI circuits (10 ∼ 8-μm PMOS LSI circuits in 1969–1971) until almost reaching its limit, and 3D vertical integration has started just recently to extend Moore’s law. In the course of this development, there have been so many severe problems to overcome in every new generation, and many new ideas have been proposed to solved them.

Figure 1. A brief history of transistor/LSI development. PCT: point-contact transistor.

The year 2022 was the 75th anniversary of the transistor invention, and I have written a number of articles related to the history of transistor inventions [2], [3], [4], [5], [6], [7]. In this article, I explain my experience of actually developing LSI products and their technologies at Toshiba during 26 years (1973–1999), using historical photographs and illustrations.

My LSI Circuit Development at Toshiba From 1973 to 1999

Toshiba used to be one of the world-leading companies for its seminal LSI technologies over the last quarter of the 20th century. Those technologies include the first CMOS microprocessors for electric calculators, by Y. Suzuki, in the early 1970s; the first automobile engine control 12-bit microprocessors, installed in the Lincoln Versailles in the late 1970s; one of the world’s first 1-Mb CMOS DRAMs, which dominated the global market in the late 1980s; and the invention of NAND flash memory, by F. Masuoka, at the end of the 1980s. Most of these great achievements were brought about not by the order of superiors but by the spontaneous ideas and enthusiasm of young engineers. At that time, the LSI industry was very young and rapidly growing, and every company was full of young engineers who started their career within several years of one another. During that period, Toshiba, as well as some other companies, had a corporate culture that allowed engineers to implement their ideas, spending a certain number of resources based on their own judgment, even if disapproved by their superiors, as long as they satisfactorily fulfilled their assigned responsibilities.

Figure 2 illustrates technology developments that I participated in at Toshiba. I joined Toshiba in 1973—immediately after the IC Laboratory, headed by Y. Takeishi, was founded in the R&D Center to enhance the development of silicon (Si) LSI technologies—and I retired from the Semiconductor Division in 1999. Before the foundation of the IC Laboratory, Toshiba was slightly behind in the development of mainstream LSI technologies, while advancing in the development of relatively special and unique IC/LSI technologies at that time, such as CMOS microprocessors and EPROMs.

Figure 2. The author’s LSI development experience at Toshiba. Al: aluminum; BPSG: borophosphosilicate glass; CVD: chemical vapor deposition; ECAD: electronic CAD; RTA: rapid thermal annealing; NiSi salicide: nickel mono-silicide self-aligned silicide; SiO_xN_y: silicon oxynitride.

Development of the First Toshiba NMOS LSI Technology

My first job at Toshiba was the development of Toshiba’s first NMOS LSI technology with 1-kb SRAMs as a concept product, and I was appointed to lead a team consisting of several engineers and technicians, in 1974. NMOS LSI was the second generation of the LSI, after the first generation of the PMOS LSI, and the design rule shrank from 8 to 6 μm.

At that period, the structure of LSI was very simple compared with recent nano-CMOS, as demonstrated in Figure 3. The number of elements necessary for the chip was only five. There were only eight layers for the LSI, including the Si substrate, and the number of mask steps was only seven. They were 1) active area formation, 2) D (depletion)-type channel ion implantation, 3) direct contact between the poly-Si and Si substrate, 4) the poly-Si gate electrode, 5) the contact hole, 6) aluminum (Al) interconnects, and 7) the bonding pad opening.

Figure 3. A cross section of Toshiba’s first NMOS LSI. (a) Cross section, (b) magnified cross section, and (c) layers, materials, and elements used. SiO₂: Si dioxide.

For the second-generation LSIs, ED logic circuits—a D-type n-MOSFET load with an E (enhancement)-type n-MOSFET driver [8]—were chosen by most of the companies, including us, because of their superior input-to-output transfer characteristics. Here, D type means negative V_th (threshold voltage) with normally-on operation, and E type means positive V_th with normally-off operation. Precise control of V_th by channel ion implantation had just started in the early 1970s, enabling the realization of E-type n-MOSFETs easily, which used to be difficult due to the existence of the positive Si/SiO₂ interfacial charge. In our process, E-type channel ion (B) implantation was carried out for the entire wafer without a mask before the D-type implantation. Then, the D-type implantation (P) was performed with masking of the E-type MOSFET areas.

Figure 4 presents Toshiba’s 1-kb NMOS SRAMs: TMM311P and 312P [9]. The device parameters were as follows: gate length: 6 μm; gate SiO₂ thickness: 100 nm; source/drain junction depth: 1.7–1.8 μm (${\rho}_{s}$ = 6 Ω/sq); V_th(E) = 0.9 V ± 0.2 V; V_th(D) = −3 V ± 0.6 V; V_th(Field) = 20 V; ${\rho}_{s}$ (poly-Si) = 20–40/Ω sq; cell size: 66 × 80 μm²; chip size: 3.16 × 3.72 mm²; access time: 300 ns; cycle time: 600 ns; power supply: 5 V; and power dissipation: 250 mW.

Figure 4. Toshiba 1-kb SRAMs. (a) Chip photograph. (b) Package and wafer photographs.

Prior to the NMOS 1-kb SRAMs, Toshiba produced a 256-b SRAM with an 8-μm Al gate PMOS LSI technology. The NMOS 1-kb SRAMs adopted Si gate technology. At Toshiba, Si gate technology was already introduced, by H. Iizuka and F. Masuoka, in 1972–1973, to the company’s stacked double-poly-Si gate structure for EEPROMs with a PMOS LSI technology [10]. My first experimental work at Toshiba in 1973 was to optimize the 6-μm poly-Si gate electrode etching. I adopted a 40-nm thermally grown SiO₂ of poly-Si as the etching mask and determined the optimum composition of the etching solution for reducing the lateral etching to suppress the variation of the poly-Si gate length as HF 30 cc: HNO₃ 300 cc: CH₃COOH: 450 cc, I₂: 100 mg.

In the course of the development, a number of unexpected severe problems occurred, as described in the following.

Al Penetration (Spike) Problem

Electron beam irradiation to an Al target to evaporate Al had been used for the Al film deposition. X-ray irradiation generated by the electron beam broke the atomic bonds at the Si/SiO₂ interface and shifted V_th. Hydrogen annealing, called sinter, in forming gas (N₂:H₂ = 9:1) ambient at 450–500 °C, had been used to recover the V_th shift as well as to secure a good Al-to-Si contact. When starting the 6-μm NMOS technology development, there had often been short circuit failures between the drain and the substrate [Figure 5(c)]. This did not occur in the 8-μm process with the larger junction depth. At first, the cause was thought to be Al intrusion into the Si because of the silicide reaction. However, it was confirmed that Si atoms diffuse into the Al line at high temperature [Figure 5(a) and (d)], creating pits at the edge of the contact hole [Figure 5(b)] [11]. The immediate solution was to change the Al interconnect layout design to impede the Si diffusion, such as providing a slit against the diffusion path. Then, we introduced Al–Si (1%) as the evaporation target to saturate the Si concentration in the Al before the sinter process so as to suppress the Si diffusion.

Figure 5. The Al penetration (spike). (a) Si diffusion paths in Al, (b) contact hole after removing Al, (c) short circuit failure rate, and (d) Auger measurement of the Si concentration along the Al line.

Nonuniform Etching

Another big problem at the early stage of the development was nonuniform etching of SiO₂ film [Figure 6(a)]. In the 1970s, most of the etching was conducted by liquid etchant. In addition to nonuniform etching, there were some strangely shaped residuals, such as polygon and dendritic shapes. The cause of the nonuniform etching could not be figured out for a few months despite intensive investigations day and night. One day, I observed that the center of a wafer was shining with a pearl color in the etchant and found that the nonuniform etching appeared only in the shiny area, under microscope inspection, after the etching. The shining was caused by room light reflection of the air bubbles on the wafer [Figure 6(b)], and this was confirmed because the shining disappeared by lifting up the wafer to the air and dipping it again. The polygon- and dendritic-shaped residuals were found to be caused by the precipitation of ammonium fluoride crystals in the bubbles. It was also confirmed that thicker resist film wafers easily attracted the bubbles [Figure 6(c)]. Because it was difficult to decrease the resist thickness considering the resist defect density, the immediate solution was to lift up the wafer to the air to break the bubbles and then dip it again into the etchant. Soon, we developed bubble prevention methods, such as dipping wafers into the surfactant solution before the etching and a wafer rotation system in the etchant to remove the bubbles.

Figure 6. Nonuniform etching. (a) A microphotograph after etching with SiO₂ film. (b) The air bubble coverage during etching. (c) The air bubble wafer distribution versus the resist thickness. HF: hydrogen fluoride; NH₄F: ammonium fluoride; H₂O: water.

Chip Yield and Photolithography Failure by CVD Particles

Figure 7 shows the 1-kb SRAM chip yield trend until the first commercial production. During that period, 21 test lots—typically consisting of 23 wafers per lot, with 140 chips per wafer—were fabricated for the examination and improvement of circuit performance, process conditions, and reliability characteristics. The mask design change/refinement was conducted six times. In the mid-1970s, a 40% chip yield at the die sort (wafer test) and a 70% package-assembled yield were assumed to be satisfactory levels for profitability. It took 18 months until the chip yield stabilized to about 40%. Then, microscope analysis of the SRAM failure bits was conducted for a typical wafer. The causes of 89 failures on a wafer were classified: photolithography pattern failures (including those caused by CVD practices): 32; CVD particles themselves: 12; scratches in the wafer peripheral: 13; and unknown: 8.

Figure 7. The NMOS 1-kb SRAM wafer yield trend. BT: bias temperature; LOCOS: local oxidation of Si; DAT: design approval test.

The existence of CVD particles on the patterns often led to fatal errors [Figure 8(a)], but this also caused pattern failures during the photolithography process, as detailed in Figure 8(b) and (c). The mask contact on the wafer crushed the particles, resulting in distortions of the resist and etched patterns. Furthermore, the debris of the crushed particles and the resist stuck to the mask, causing pattern failures for the next wafer photolithography. The solution was to increase the frequency of the clearing of CVD equipment and photolithography masks. However, the production line had to consider the tradeoff between the machine operation time and the chip yield. The particle-oriented failures were slightly mitigated by primitive methods, such as wafer wiping by cotton swabs and precrushing particles with a dummy glass mask, followed by wafer washing. The mask dirt problem was completely solved by the introduction of projection-type mask aligners, such as the Perkin–Elmer Micralign projection aligner, in the late 1970s.

Figure 8. CVD particles and photolithography pattern failure. (a) CVD particles. (b) The deformed resist and dirtied mask with crushed particles because of contact mask alignment. (c) The resist pattern failure caused by particles.

Introduction of Borophosphosilicate Glass Reflow

Thinning and disconnection of Al interconnects at the steps had caused reliability problems (Figure 9). Although phosphosilicate glass (PSG) reflow [12] had already been introduced by some other companies to smooth the steps, we chose borophosphosilicate (BPSG) reflow (Figure 9). Moisture absorption of PSG film with a high P concentration had sometimes caused an Al corrosion problem. While a P concentration of 2.7 × 10²¹/cm³ and 30-min anneal at 1,000 °C was necessary for the PSG reflow, a P concentration of 2.6 × 10²⁰/cm³ with a B concentration of 2.2 × 10²¹/cm³ and 15-min anneal at 1,000 °C was found to be sufficient for the BPSG reflow. A one-order-of-magnitude smaller P concentration suppressed the hygroscopicity of the film and decreased the possibility of Al corrosion. We introduced BPSG reflow to the product in 1976, and probably this was the first in the world.

Figure 9. The (a) Al interconnects at the step and (b) step smoothing by BPSG reflow.

Field Leakage Failure at Bias Temperature Test With Plastic Package

In September 1975, I/O leakage failure occurred at the bias temperature test when chips were assembled in plastic packages. This leakage was caused by the parasitic field MOSFET (field-MOS) turning on due to migrated charges from the plastic. This kind of field leakage had not happened for the previous 8-µm PMOS LSI technologies because of the higher field-MOS V_th—even without impurity doping—due to the positive Si/SiO₂ interface charges. For NMOS LSI, the field-MOS V_th was determined by the B implantation used for setting the n-MOSFET V_th (0.9 V) and could not be independently raised to more than 10 V (Figure 10). To solve this problem, we were required to increase the field B concentration independently from that of the n-MOSFET channel. Because a 2-µm space margin was necessary for the mask alignment at that time, a self-alignment process of the field B implantation to the field oxide region was indispensable. This was possible only by introducing the self-aligning local oxidation of Si field isolation technique, invented by E. Kooi, in 1970 [13], and we raised the field-MOS V_th to 20 V to solve this problem.

Figure 10. The field leakage by migrated charges from plastic packaging.

Production of 1-kb NMOS SRAMs and NMOS 12-b Microprocessor for Lincoln Engine Control

After design approval tests, including various kinds of reliability examinations, 1-kb NMOS SRAM (TMM311, 312, and 313) commercial production started in 1976 (Figure 11). Eventually, deformed 60-mm-diameter wafers—which included cutting the upper and lower portions of the wafers so that the wafers set on the quartz boat fit in the 2-in wafer furnace tube—and a ×0.9-shrunk mask were used to increase the number of chips produced to 1.4 times in total.

Figure 11. The (a) mask alignment and (b) chip assembly on the production line in the mid-1970s at Toshiba.

The NMOS version (T3517A) of the 12-b TLCS-12 microprocessors were produced using our NMOS technology and installed in the engine control unit of the 1978 model Lincoln Versailles. The first 12-b microprocessors were originally fabricated with 8-μm Al gate PMOS technology, in 1973, but Ford requested improved performance through NMOS technology for use in commercial cars. The NMOS TLCS-12 was the world-first engine control microprocessor used for commercial cars.

Development of 64-kb DRAM Technology

In 1977, our group moved to the newly founded Semiconductor Device Engineering Laboratory, headed by Y. Takeishi, in the Semiconductor Division. I was appointed team leader of NMOS 64-kb DRAM technology development and worked with the circuit design team. The minimum linewidth was 3 µm, and this was the beginning of the VLSI era. After the successful test trial of the 4-µm 64-k DRAM chip design and fabrication, in 1977 [14], the first things to determine for the commercial device were the supply voltages, circuit specification, and chip size. Although 5 V was desirable from the 3-µm technology point of view, the supply voltages were initially determined as +10 and −5 V (the back gate power supply) by the circuit team’s request, considering the number of stored charges for the DRAM capacitor. However, the world standard became the 5-V-only power supply, in 1979, and we redesigned the circuit and the process technology [15]. The chip size (3.66 × 6.8 mm²) (Figure 12), decided considering the package requirement, happened to be one of the world’s smallest among the commercial 64-kb DRAMs. Because it was difficult to store all the complicated control circuits inside of the chip through the conventional process, we introduced new technologies, including stepper photolithography and “dry processes” such as source/drain ion implantation, non-isotropic reactive ion etching (RIE), and oxygen plasma resist ashing.

Figure 12. The 64-kb DRAM (TMM4164). (a) Chip photograph. (b) Package photograph. (c) Wafer photograph.

Introduction of Stepper GCA Direct Step on Wafer for Photolithography

Toshiba purchased a kind of so-called beta machine, a Mann 4800 direct step on wafer (DSW) system, at the end of the 1970s. The 4800 DSW was the world’s first stepper conducting step-and-repeat light exposures on wafers for reduced pattern projection, using a 10:1 mask to enhance the pattern resolution. The stepper was quite a new concept, and we faced initial problems related to the new photolithography procedures as well as beta machine-related mechanical bugs. One of the biggest ones was the “common defect” problem. In that period, it was quite normal that there were one or two defects on a 1:1 mask, and this did not significantly affect the chip yield [Figure 13(a)]. However, in the case of the 10:1 mask, where only two chip patterns exist [Figure 13(b)], one or two defects decreased the yield by 50% or 100%, depending on the defect’s location [Figure 13(a)]. The mask quality was not significantly improved within a couple of years despite the mask makers’ effort, and inspection of the new masks was a huge burden of the device development engineers. Indeed, 44% of the new masks had defects in March 1980 [Figure 13(c) and (d)]. Eventually, automatic defect inspection machines were developed by several companies to reduce the human eye inspection labor. In 1981, Nikon steppers were introduced to 64-k DRAM development and later used for production.

Figure 13. The common stepper defect problem. (a) The projected mask defects for 1:1 and 10:1 masks. (b) The 10:1 Al interconnect pattern mask. (c) The mask failure list in March 1980. (d) The defects on a mask and resist patterns.

Introduction of “Dry Process” (RIE and Source/Drain Ion Implantation) to Suppress Side Etching and Side Diffusions

To integrate many components within a chip, suppression of the side etching of lines and side diffusion of impurities is important. We introduced RIE and source/drain ion implantation to integrate a large number of circuits components in a small chip. These technologies were called “dry process,” in comparison with the conventional “wet process” consisting of liquid etching and gas phase diffusion. We were one of the first to introduced the dry process to VLSI production.

As expected, there were several initial problems for the introduction of the dry process, such as resist film hardening due to ion bombardment and fluorocarbon film deposition as the reactive ion byproduct. The removal of those films was often not easy, even when introducing another dry process, resist ashing, for film removal using oxygen plasma. One of the biggest initial problems of RIE involved Si residues after the poly-Si RIE (Figure 14). The causes were soon found to be tiny etching-resistant areas made of some kind of oxides and/or fluorocarbons. Because of the small side etching nature of RIE, even a very tiny etching mask prevents the complete etching off of the poly-Si under it. It took more than a few months to completely solve the problem by enhancing the poly-Si surface cleaning process and tuning the RIE side etching conditions, resulting in the delay of the DRAM development schedule.

Figure 14. The poly-Si gate electrode RIE and residue.

Before the 64-kb DRAM generation, source/drain P (phosphorus) doping had been conducted by gas phase phosphorus oxychloride (POCl₃) furnace diffusion. For the 64-kb DRAM, arsenic (As) ion implantation of 5 × 10¹⁵ cm⁻² at 40 keV, by a Lintott high-current beam ion implanter, was adopted in experiments. A junction depth of <0.45 μm with a sheet resistance of <40Ω/sq was obtained. Ion implantation had been used since the early 1970s for the channel doping to adjust the V_th of MOSFETs, but the typical dose was only 10^11–12 cm⁻² with around 100 keV of acceleration energy. The three-orders-of-magnitude-larger ion dose and the As ions, being twice heavier than the P ions, were prior concerns for junction damage, but fortunately, no significant junction leakage was confirmed by the experiments.

Discovery of Plasma-Induced Damage That Caused Bit Errors

At the end of July 1980, the development of 64-kb DRAM reached a stage where the majority of the chip failure modes was roughly one to 100 bit errors. However, the bit errors continued more than several months without any significant improvement, although it was suggested that the cause was memory capacitor gate oxide breakdown from the Poisson distribution of the bit errors. By inspecting the bit error memory cell [Figure 15(a)] by removing layers, holes were observed on the memory capacitor poly-Si electrode [Figure 15(b)]. After removing all the layers, small yellow round spots were found by staining the substrate with a chemical treatment [Figure 15(c) and (d)]. The yellow spots were found to be n⁺ Si pillars grown by the local melting of the n⁺ poly-Si gate electrode through gate oxide breakdown.

Figure 15. The bit error caused by PID. (a) A DRAM cell. (b) A hole on the poly-Si capacitor. (c) and (d) Yellow spots (the P-diffused region). (e) A Si pillar created by the gate oxide breakdown.

The gate oxide breakdown was caused by the accumulated charges at the poly-Si gate electrode by the ion bombardment during RIE and source/drain high-dose ion implantation (Figure 16). The problem was solved by tuning the ion bombardment process conditions. This was probably the world’s first observation of plasma-induced damage (PID) and was published as a late-news letter at an Electrochemical Society meeting in fall 1982 [16]. PID became a worldwide problem in the late 1980s.

Figure 16. The mechanism of plasma-induced damage.

Other Issues

CVD particles had been recognized as the major cause of yield degradation since the middle of the 1970s. For 64-kb DRAM production, various kinds of dusts (Figure 17) originating from wafer process and clean room environments were found to be a big problem causing significant yield degradation. Unfortunately, the clean room facility used for development and early production was not suitable to decrease the dust level. As a result, a huge number of resources were invested for the next generations of DRAMs to significantly improve the facility.

Figure 17. The various kinds of dusts on the 64-kb DRAM wafer. (a) A CVD particle. (b) A resist flake. (c) A poly-Si fragment.

Degradation of the charge retention due to various causes, such as heavy metals, carrier migration, and carrier generation by alpha particle radiation [17], were the concern. We introduced an intrinsic gettering wafer, in 1981, to suppress those degradations [18], [19]. The alpha particle-induced soft error was solved by coating the chip with a pure polyimide film.

Another big problem was the accuracy of the circuit design. At that time, the circuit simulation ability at Toshiba was not sufficient to simulate the NMOS enhancement-type MOSFET driver and enhancement MOSFET load (EE) logic circuit [20] used for the DRAM. The output level and switching time of the EE logic gate were quite dependent on the MOSFET geometry and characteristics and, thus, more complicated than those of CMOS logic. To reach the satisfactory level of the commercial DRAM specifications, 20 mask refinements, with each verification by device fabrications, were required. Through the development of the 64-kb DRAM, Toshiba established the VLSI production technologies—including stepper lithography and dry process—earlier than other companies, and learned about the importance of investing huge resources to the development and mass-production facility. Toshiba also recognized the difficulty of designing NMOS EE circuits. The earlier establishment of the VLSI production technology, and lessons learned from the development of 64-kb DRAM made a great success of Toshiba’s 1M bit CMOS DRAM that almost monopolized the world market in the late 1980s.

Small Geometry MOSFET Research, Technology CAD, Electronic CAD, and 1-Mb SRAM Circuit Design

From 1983 to 1986, I was out of LSI device technology development. I was sent to the IC laboratory of Stanford University as a visiting scholar from 1983 to 1984, where I proposed on-chip measurement of small geometry MOSFET capacitances and their modeling. The Xerox Palo Alto Research Center was interested in my proposal and volunteered to fabricate samples. These were the first on-chip capacitance measurement circuits, and the resolution reached, unbelievably, down to atto (10⁻¹⁸) Farad [21]. The short channel effects (SCEs) of the MOSFET capacitances were discovered for the first time, and the cause of the SCEs was clarified to be the carrier velocity saturation [22], [23]. At Stanford, I also learned deeply about technology CAD and the mathematical theory of numerical solutions. After coming back from Stanford in November 1984, I was one of four designers ordered to design CMOS 1-Mb SRAM circuits [24]. I was also appointed in 1985 to lead a small team introducing an electronic CAD system for Toshiba memory design and chose Solomon Design Automation (SDA) Systems as the software and the Sun-2 engineering workstation as the hardware. Later, SDA was acquired by Cadence and became almost the world standard.

Leading 0.5-µm Logic CMOS, 1.2/0.8-µm Logic BICMOS, and 0.8-µm Mixed Logic and SRAM CMOS Development

In October 1986, I was appointed the leader of three teams: 0.5-µm logic CMOS, 1.2/0.8-µm BiCMOS [25], and 0.8-µm mixed logic and SRAM technologies. In the late 1980s, BiCMOS was the highest-performance logic technology, used, for example, in Intel’s Pentium microprocessor. To realize a highly activated shallow impurity profile for the bipolar transistor, we introduced rapid thermal annealing (RTA), in 1989 [26], [27]. For the logic CMOS, hot carrier reliability degradation was one of the major concerns due to the electric field increase with the device size reduction. We conducted an intensive study of hot carrier-induced degradation [28], [29], [30]. Another new technology was the introduction of WSi_x polycide (stacked WSi_x and poly-Si) to decrease the poly-Si gate electrode resistance. The introduction of new materials was not easy, and there were problems of peeling of films caused by the thermal expansion difference (Figure 18) and impurity interdiffusion between n⁺ and p⁺ poly-Si regions through the WSi_x film [31].

Figure 18. The WSi_x film peeling. (a) Microphotograph. (b) SEM photograph.

Sub-50-nm CMOS Technology Development

In 1989, I moved to the ULSI Research Center, headed by Y. Takeishi, which had been founded as a corporate laboratory several years before, and I became the group manager of developing advanced logic CMOS and RF bipolar/BiCMOS technologies.

Prediction of CMOS Scaling

At the beginning of the 1990s, it was briefly imagined that the CMOS scaling limit could be about 0.1–0.07 µm [32] because of several reasons, such as difficulty in suppressing the leakage current, parasitic resistance increase, and V_th variation. But there was no proof and no deep understanding of device physics in the deep-sub-0.1 µm region. We conducted detailed analysis using Monte Carlo simulation, collaborating with the University of Bologna, from 1992 and published a new scaling scheme (or new roadmap) in 1993 (Figure 19) [33]. We predicted that a retrograde channel doping structure, such as one made by nondoped epitaxial growth, could operate at room temperature until gate length L_g = 25 nm and that, in case of double-gate MOSFETs [34], L_g could be scaled to below the 25-nm region. We also predicted the introduction of a high-k gate insulator from sub-50-nm generation. Later, Intel introduced high-k in 45-nm technology [35] and a FinFET (a vertical-type double-gate MOSFET) at 22 nm [36]. These facts proved that the predictions in our new scaling scheme were quite appropriate.

Figure 19. The CMOS scaling roadmap by Monte Carlo simulation published in 1993. (a) The MOSFET structures. (b) The scaling limit. (c) The roadmap for the supply voltage and gate oxide thickness.

Fabrication of 40-nm-Gate-Length MOSFETs

To verify the operation of sub-50-nm MOSFETs, we fabricated 40-nm-L_g MOSFETs [37]. At that time, there was no stepper to realize the 40-nm photolithography and no shallow ion implanter for 10-nm junction depth with low resistivity. We selected a resist slimming technique [38] for the stepper photolithography and P (phosphorus) solid-state diffusion from the PSG gate sidewall by RTA [Figure 20(a) and (b)]. The realization of the 10-nm shallow junction with low resistance (6 kΩ/sq) [Figure 20(c)] was the key for the operation. It was confirmed that 40-nm-L_g n-MOSFETs operate with high performance at room temperature [Figure 20(d)]. The ${\sigma}$ (standard deviation) of V_th distribution in a wafer was as small as 0.05 V, even at a high V_d = 2 V. The demonstration of these experimental results broke the “red brick wall” of the scaling limit and kept the traditional scaling trend [39], [40], [41] (Figure 21).

Figure 20. The fabrication of 40-nm-gate-length n-MOSFETs. (a) Cross section. (b) Top view by scanning electron micrography (SEM). (c) Impurity depth profile measured by secondary ion mass spectrometry (SIMS). (d) Electrical characteristics.

Figure 21. The gate length scaling trend.

Introduction of 1.5-nm SiO₂ Gate Insulator

We used 3-nm-thick gate SiO₂ for the fabrication of the 40-nm-L_g MOSFETs, due to concern about direct tunneling gate leakage (I_g) below 3 nm [Figure 22(a) and (b) [42]]. However, during our ultrathin Si oxynitride (SiO_xN_y) gate insulator MOSFET experiment in 1991, we had experienced a decrease in the ratio of I_g to the drain current (I_d) with L_g reduction. We challenged the 1.5-nm-gate SiO₂ MOSFET in 1994 [42], [43]. The 1.5-nm SiO₂ film was grown by rapid thermal oxidation (RTO). The ultrathin SiO₂ was quite uniform [Figure 23(a)] due to the strong oxidation of Si at the high RTO temperature at the early stage of the oxidation, preventing the local thinning (defect or variation) of the SiO₂ film. The ${\sigma}$ of the SiO₂ thickness in an entire wafer evaluated by MOS capacitor I_g was only 0.008 nm [44]. With decreasing L_g below 1 μm, I_g became ignorable compared with I_d [Figure 23(b)]. We confirmed a world record transconductance value of 1,010 mS/mm at V_d = 1.5 V and L_g = 90 nm [42], [43].

Figure 22. The significant leakage current from the direct tunneling of the SiO₂ gate oxide. (a) The direct tunneling leakage current mechanism. (b) The l_g–V_g characteristics of 100 × 110-µm MOS capacitors.

Figure 23. The introduction of the direct tunneling of the SiO₂ gate oxide. (a) A TEM photograph of 1.5-nm SiO₂ grown by RTO. (b) The normal operation of a 1.5-nm-gate SiO₂ MOSFET.

The successful results of our direct tunneling gate oxide MOSFETs with manufacturability and reliability [44] changed the international technology roadmap for semiconductors (ITRS) (Figure 24).

Figure 24. The (a) gate insulator thickness trends predicted by the ITRS and (b) real trends, with materials and thicknesses.

Demonstration of the 40-nm-gate-length MOSFETs and the 1.5-nm-thick-gate SiO₂ MOSFETs as well as our new scaling scheme by Monte Carlo simulation had a great impact on the world semiconductor industry and enhanced the development of nano-CMOS technologies aggressively beyond the red brick wall of 0.1 µm.

Introduction of New Materials, Such as Oxinitride Gate Insulator and Nickel Silicide

Toward the nano-MOS generations, we introduced new materials ahead of other companies at the beginning of 1990s. One was the development of the SiO_xN_y gate insulator made by rapid thermal nitridation (RTN) for the suppression of B penetration (or diffusion), in 1990 [45]. The penetration occurs only for the p-type dopant of poly-Si gate and not for the n-type dopant. We demonstrated that several percent of the nitrogen atoms in the SiO₂ film effectively suppresses the B penetration (Figure 25).

Figure 25. The suppression of B penetration by SiO_xN_y gate film made by RTN. (a) The B penetration. (b) The l_d–V_g characteristics. (c) The N concentration profile by Auger spectroscopy. (d) The B concentration profile by mass spectrometry.

Traditionally titanium disilicide (TiSi₂) had been used for salicide (self-aligned silicide for the source, gate, and drain [46], [47]) to reduce resistances. The silicidation reaction of the metal film does not take place on the field SiO₂ and Si nitride (Si₃N₄) gate sidewall. Thus, the self-alignment of the silicide on Si regions can be conducted by removing the unreacted metal on the SiO₂ and Si₃N₄ with an acid solution (Figure 26). There had been many problems, such as agglomeration of the silicide, bridging, and junction leakage. We chose nickel mono-silicide (NiSi) and developed NiSi salicide technology in 1991 (Figure 27) [48], [49]. The Ni silicidation mechanism that Ni diffuses into Si to form the silicide [as opposed to the Ti case (Figure 27(a)] completely solved the bridging and agglomeration problems [Figure 27(b)]. Furthermore, NiSi is suitable for shallow junctions because of less Si consumption during the silicidation because of the monosilicide. We were the first to develop NiSi salicide CMOS technologies, and they became the world standard from the end of 1990s until the late 2000s, when the high-k/metal gate stack was introduced.

Figure 26. The structure of salicide (self-aligning the silicide to the source/gate/drain) and its problems. Unreacted metal films on the gate sidewall and field oxides are removed by an acid solution.

Figure 27. The NiSi salicide. (a) The silicidation mechanism difference between TiSi₂ and NiSi. (b) TEM photographs of the cross section and top of the TiSi₂ and NiSi gate electrodes. (c) A SEM cross section of an NiSi salicide CMOS.

Development of RF CMOS Technology

AC characteristics MOSFETs had not been suitable for RF applications, but we noticed that the RF performance of CMOS was expected to be greatly improved by scaling [50] and launched an RF CMOS development project, with collaboration from KU Leuven and ETH Zurich in the mid-1990s. We obtained a world record Si MOSFET f_T value of 245 GHz by the end of the 1990s [51]. In 1998, our group moved to Microelectronics Engineering Laboratories, headed by Y. Unno, in the Semiconductor Division and published an RF CMOS roadmap, including the gate finger length optimization for f_T, f_max, and noise figure for each generation [52]. From 1998, we started a collaboration with Erickson to extract the 150-nm RF CMOS parameters for circuit design, contributing to the development of Bluetooth [53]. Now, nano-CMOS has become the mainstream technology for RF front-end circuits for 4G and 5G applications.

Conclusion

LSI technology evolution from the 6-µm NMOS to the recent nano-CMOS was described based on my experience at Toshiba from 1973 to 1999. Unexpected problems often happened, resulting in severe yield degradation and delays in development schedules. It required many hours of hard work to survive the tough competition among strong rival semiconductor companies. However, the severe problems and competitions have been the source of innovations and evolutions. LSI technology development was a really exciting and rewarding job, having contributed to the realization of the superintelligent society.

Acknowledgment

The accomplishments were the results of the teamwork of all the members, and I would like to sincerely appreciate them, some of whose names appear as the coauthors of the references. Finally, I would like to express appreciation to my superiors at Toshiba: Y. Takeishi, M. Toyama, Y. Nishi, S. Horiuchi, S. Kohyama, N. Goto, Y. Unno, A. Kasami, and S. Komatsu, as well as Prof. T. Sugano (University of Tokyo) and R. Dutton (Stanford University) for their occasional precious advice guiding me to a professional engineer.

Biography

Hiroshi Iwai (h.iwai@ieee.org) has been a semiconductor device engineer working in the field of LSI and its technology development for 50 years, since 1973. He received his B.E. and Ph.D. degrees from the University of Tokyo. He joined Toshiba in 1973 and moved to the Tokyo Institute of Technology, Yokohama, Kanagawa, 226-8503, Japan, in 1999. He is now a professor emeritus at the Tokyo Institute of Technology and a vice dean and distinguished chair professor at National Yang Ming Chiao Tung University, Hsinchu City, 300093, Taiwan. He served as IEEE Electron Devices Society (EDS) president and IEEE Division I director. He is an EDS Eminent Lecturer, a Life Fellow of IEEE, and a committee member of IEEE International Roadmap for Devices and Systems.

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Digital Object Identifier 10.1109/MED.2023.3259978

Date of current version: 28 June 2023

IEEE Electron Devices Magazine—A New EDS Member Benefit

Ravi Todi, IEEE Electron Devices Society president

I am extremely honored and pleased to write this message for the inaugural issue of IEEE Electron Devices Magazine (ED-M) as the IEEE Electron Devices Society (EDS) president. This issue of IEEE ED-M is dedicated to the celebration of the 75th anniversary of the invention of the mighty little transistor. The invention of the point-contact transistor on 16 December 1947 and the BJT on 23 January 1948 revolutionized the semiconductor industry worldwide and brought profound changes to humanity. Over the past 75 years, the transistor’s device structure and fabrication technology have continuously evolved from the “point-contact” transistor to the state-of-the-art, ultrathin-body FET. This continuous evolution of transistor architecture and disruptive innovation of IC fabrication processes led to the production of high-performance, low-power, high-density, and low-cost VLSI circuits and systems or IC chips, enabling smart environments and integrated ecosystems. The relentless pursuit of worldwide R&D on electron devices continues to produce high-performance devices that continuously improve computational efficiency and computing power that support wireless communication technology and 5G and Beyond, not to mention computationally intelligent devices that support artificial intelligence and machine learning. Later this year, a commemorative volume, “75th Anniversary of the Transistor,” will be published to celebrate the 75th anniversary of the invention of the transistor and provide comprehensive coverage of the historical, underlying perspective of the invention of the transistor and its subsequent evolutions.

EDS is truly an international Society with more than 11,000 members and more than 250 local Chapters worldwide. Over the past seven decades, EDS has been true to its vision of promoting excellence in the field of electron devices for the benefit of humanity. EDS is a volunteer-led organization with the mission to foster professional growth of its members by satisfying their needs for easy access to and exchange of technical information, publishing, and education and technical recognition, while enhancing public visibility in the field of electron devices. As EDS is an all-volunteer Society, the selfless dedication of our volunteers is of utmost importance for the well-being of our Society. Our volunteers organize our conferences and workshops, and lead our education programs, including webinars, distinguished lecture series, and tutorials. Our volunteers help make our publications one of the best within our field by serving as reviewers and editors. Our volunteers help shape the scope of our technical committees by serving on various technical committees, and finally, our volunteers serve in various governing roles like Chapter officers, Society board and forum members, committee chairs, executive committee members, and Society officers. I encourage every reader to connect with EDS, your professional Society, and help volunteer to lead the future our of Society.

Finally, I take this opportunity to acknowledge the dedication and visionary leadership of past EDS volunteer leaders who have made EDS one of the premier Societies of IEEE.

Digital Object Identifier 10.1109/MED.2023.3263401

Welcome to IEEE Electron Devices Magazine

By Joachim Burghartz, Editor-in-Chief

Dear readers and members of the IEEE Electron Devices Society (EDS), it my great pleasure to introduce you to the new IEEE Electron Devices Magazine (ED-M). This new IEEE periodical comes at the right time, as we celebrate the 75th anniversary of the transistor, which has led to the evolution of microelectronics industry and applications. The EDS has been a part of this fascinating journey, and its flagship periodicals and joint publications provide a platform for displaying the newest innovations on the way. But there is more to it. Electron devices and their consumer and industrial applications are intensely impacting our work and personal lifestyles, urban and natural environments, transportation, communication, and security and safety. Clearly, there are humanitarian, societal, and environmental issues to be discussed. Electron devices drive industries in need of highly educated engineers and technicians, with a particular need for more women in engineering. Therefore, education in electron device engineering at all levels is an important aspect to pay attention to. ED-M is launched to provide a platform for addressing those issues. The magazine’s purpose is also to publish tutorials that provide easy entry to a specific electron device topic and to offer reviews of selected electron devices aspects and applications. There will be standing, invited, and contributed columns through which renowned experts as well as ED-M readers can share their work. And there will be articles on people, IEEE and EDS news. We intend this magazine to be as interactive as possible, for which purpose you will have the opportunity to offer your thoughts and comments in our “Letters to the Editor” column.

Each ED-M issue will have a feature topic consisting of several long articles and be organized by a guest editor or by an ED-M editor. Submissions are invited and contributed and will be peer reviewed. The articles published are intended to be comprehensive and targeted at both the general electron device engineer and the specialist. ED-M is fully sponsored by the EDS, so there is no publishing fee for authors. There is also good news for readers: Members of the EDS will receive a complimentary copy of ED-M with their membership; printed copies can be ordered, with a charge for printing and shipping. Members of other IEEE Societies and Councils can subscribe for a small fee. In the magazine’s first year, EDS members will even receive free printed and shipped copies.

This very first issue of ED-M has the 75th anniversary of the transistor as a feature topic. Much has already been published and said recently about that major invention. Therefore, this ED-M issue is devoted to the people driving semiconductor research and development. We hope that this inaugural issue will be well received by you as readers and EDS members, and serve as an incentive for you to submit your articles and columns or to serve as a guest editor.

Digital Object Identifier 10.1109/MED.2023.3261083

Date of current version: 28 June 2023

IEEE ELECTRON DEVICES SOCIETY

President

Ravi Todi

Western Digital Technologies

E-mail: rtodi@ieee.org

President-Elect

Bin Zhao

Freescale Semiconductor

E-mail: bin.zhao@ieee.org

Treasurer

Roger Booth

Qualcomm

E-mail: boothrog@yahoo.com

Secretary

M.K. Radhakrishnan

NanoRel

E-mail: radhakrishnan@ieee.org

Sr. Past President

Fernando Guarin

GlobalFoundries

E-mail: fernando.guarin@ieee.org

Vice President of Education

Navakanta Bhat

Indian Institute of Science

E-mail: navakant@gmail.com

Vice President of Meetings

Kazunari Ishimaru

Kioxia Corporation

E-mail: kazu.ishimaru@kioxia.com

Vice President of Membership and Services

Merlyne de Souza

University of Sheffield

E-mail: m.desouza@sheffield.ac.uk

Vice President of Publications and Products

Arokia Nathan

University of Cambridge

E-mail: an299@cam.ac.uk

Vice President of Regions/Chapters

Murty Polavarapu

Space Electronics Solutions

E-mail: murtyp@ieee.org

Vice President of Strategic Directions

Doug P. Verret

IEEE Fellow

E-mail: dougverret@gmail.com

Vice President of Technical Committees

John Dallessase

University of Illinois at Urbana-Champaign

E-mail: jdallesa@illinois.edu

EDS Board of Governors (BoG) Elected Members-at-Large

Elected for a three-year term (maximum two terms) with ‘full’ voting privileges

2023 Term

Roger Booth (2)

Xiojun Guo (1)

Edmundo Gutierrez (2)

Francesca Iacopi (1)

Benjamin Iniguez (2)

P. Susthitha Menon (1)

Manoj Saxena (2)

Sumant Sood (2)

2024 Term

Mario Aleman (1)

Paul Berger (2)

Yogesh Chauhan (1)

Maria De Souza (2)

Patrick Fay (2)

Kazunari Ishimaru (2)

William Nehrer (2)

2025 Term

Constantin Bulucea (2)

Daniel Camacho (2)

John Dallesasse (2)

Mario Lanza (2)

Lluis Marsal (1)

Geok Ng (2)

Mayank Shrivastava (1)

MAGAZINE editorial staff

Editor-In-Chief

Joachim N. Burghartz

IMS CHIPS

E-mail: ed-m-editor@ieee.org

IEEE Electron Devices Magazine Advisory Board

CHAIR

Arokia Nathan

COMMITTEE MEMBERS

John Dallesasse

E-mail: jdallesa@illinois.edu

Giovanni Ghione

E-mail: giovanni.ghione@polito.it

M. K. Radhakrishnan

E-mail: radhakrishnan@ieee.org

Manoj Saxena

E-mail: msaxena@ieee.org

Ravi M. Todi

E-mail: rtodi@ieee.org

Daniel Tomaszewski

E-mail: daniel.tomaszewski@imif.lukasiewicz.gov.pl

Douglas P. Verret

E-mail: dougverret@gmail.com

Bin Zhao

E-mail: bin.zhao@ieee.org

IEEE PUBLISHING OPERATIONS

Shannon Campos

Senior Journals Production Manager

Katie Sullivan

Senior Manager Journals

Production

Janet Dudar

Senior Art Director

Gail A. Schnitzer

Associate Art Director

Theresa L. Smith

Production Coordinator

Felicia Spagnoli

Advertising Production Manager

Peter M. Tuohy

Director, Production Services

Kevin Lisankie

Director, Editorial Services

Dawn M. Melley

Senior Director, Publishing Operations

Contributions Welcome

Readers are encouraged to submit news items concerning the Society and its members. Please send your ideas/articles directly to either Editor-in-Chief or the Regional Editor for your region. The e-mail addresses of all Regional Editors are listed on this page. E-mail is the preferred form of submission.

Digital Object Identifier 10.1109/MED.2023.3273481

IEEE Electron Devices Society Magazine (ISSN 2832-7683) is published in June, September, and December by the Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016. Responsibility for the contents rests upon the authors and not upon the IEEE, the Society, or its members. To order individual copies for members and nonmembers, please e-mail the IEEE Contact Center at contactcenter@ieee.org. Member and nonmember subscription prices available on request. Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limits of the U.S. Copyright law for private use of patrons provided the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01970 U.S.A. For other copying, reprint, or republication permission, write to: Copyrights and Permissions Department, IEEE Service Center, 445 Hoes Lane, Piscataway NJ 08854, U.S.A. Copyright © 2023 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Periodicals postage paid at New York, NY, and at additional mailing offices. Postmaster: Send address changes to IEEE Electron Devices Magazine, IEEE, 445 Hoes Lane, Piscataway, NJ 08854 U.S.A. IEEE prohibits discrimination, harassment and bullying. For more information visit http://www.ieee.org/nondiscrimination. Printed in U.S.A.

Silicon Earth

Title

Silicon Earth: A Historical Perspective on the Invention/Discovery of the Transistor

What History Can Teach Us

The Uniqueness of Microelectronics

The Invention/Discovery of the Transistor

Acknowledgment

Biography

References

IEEE ELECTRON DEVICES MAGAZINE June 2023

Title

Working for William Shockley - In Memoriam: Adolf Goetzberger

Biography

References

IEEE ELECTRON DEVICES MAGAZINE June 2023

Title

Echoes of the Past: A Journey to Re-Create the Invention of the Transistor and the Earliest Transistor Circuit: Appreciating the Technical Challenges and Genius of Bardeen and Brattain

Introduction

The Point-Contact Transistor

History Repeats Itself—Following the Path of Discovery

Chasing Alpha—Benchmarking Relative to Bardeen and Brattain

A More Interesting Demo—Lessons From the Oscillator-Amplifier Box (“Bardeen Music Box”)

How Dry I Am

Final Observations

Acknowledgment

Biographies

References

IEEE ELECTRON DEVICES MAGAZINE June 2023

Title

Hermann K. Gummel and His Unique Legacy in the Field of CAD Technology for Integrated Electronics: Six Former Coworkers Remember and Reminisce

Introduction

Numerical Device Modeling

Numerical Calculation of Multiterminal Resistances and Capacitances

Compact Modeling

Electronic Design Automation

Conclusion

Biographies

References

IEEE ELECTRON DEVICES MAGAZINE June 2023

Title

Development of Modern Bipolar Transistors: A Personal Journey and Perspective

Silicon Bipolar Technology Prior to the Mid-1970s

Bipolar Transistor Device Structures

Bipolar Logic Circuits

Bipolar Technology Circa 1977

Development of Modern Si Bipolar Transistors Since 1977

Density Improvement and Capacitance Reduction Using Self-Alignment Schemes

Density Improvement and Capacitance Reduction Using Deep Trench Isolation

Dependence of Current Gain on Emitter Contact and Poly-Si Emitter

Bipolar Transistor Design, Scaling, and Pedestal Collector

Trench-Isolated Self-Aligned Bipolar Transistor Having Poly-Si Emitter and Pedestal Collector

SiGe Base Bipolar Transistors

Symmetric Lateral Bipolar Transistors on SOI

A Personal Perspective

CMOS Conquering the Digital World and Reaching Its Speed Limit

Status of Bipolar and Some Thoughts on Its Future

Biography

References

IEEE ELECTRON DEVICES MAGAZINE June 2023

Title

My LSI Development Experience at Toshiba (1973–1999): Hard Working, Exciting, and Splendid Days

Introduction

My LSI Circuit Development at Toshiba From 1973 to 1999

Development of the First Toshiba NMOS LSI Technology

Al Penetration (Spike) Problem

Nonuniform Etching

Chip Yield and Photolithography Failure by CVD Particles

Introduction of Borophosphosilicate Glass Reflow

Field Leakage Failure at Bias Temperature Test With Plastic Package

Production of 1-kb NMOS SRAMs and NMOS 12-b Microprocessor for Lincoln Engine Control

Development of 64-kb DRAM Technology

Introduction of Stepper GCA Direct Step on Wafer for Photolithography

Introduction of “Dry Process” (RIE and Source/Drain Ion Implantation) to Suppress Side Etching and Side Diffusions

Discovery of Plasma-Induced Damage That Caused Bit Errors

Other Issues

Small Geometry MOSFET Research, Technology CAD, Electronic CAD, and 1-Mb SRAM Circuit Design

Leading 0.5-µm Logic CMOS, 1.2/0.8-µm Logic BICMOS, and 0.8-µm Mixed Logic and SRAM CMOS Development

Sub-50-nm CMOS Technology Development

Prediction of CMOS Scaling

Fabrication of 40-nm-Gate-Length MOSFETs

Introduction of 1.5-nm SiO₂ Gate Insulator