Hiroshi Iwai
©SHUTTERSTOCK.COM/METAMORWORKS
The LSI technology evolution from the 6-µm NMOS to the recent nano-CMOS is described based on my experience at Toshiba from 1973 to 1999. Unexpected problems often occurred, resulting in severe yield degradation and delays in development schedules. However, the severe problems and competitions among the strong rival companies have been the source of innovations and evolutions, having contributed to the realization of the super-intelligent society.
The year 2025 will be the 100th anniversary of the invention of the Field-Effect Transistor (FET), by J.E. Lilienfeld [1]. At that time, probably no one, including him, could imagine the evolution of the FET idea to the recent nano-CMOS VLSI circuits—a typical nanoelectronic device today—that has opened up the super-intelligent human society in the 21st century. Figure 1 shows a brief history of transistor/LSI development. Device miniaturization has been continuously accomplished in the 50 years since the first-generation LSI circuits (10 ∼ 8-μm PMOS LSI circuits in 1969–1971) until almost reaching its limit, and 3D vertical integration has started just recently to extend Moore’s law. In the course of this development, there have been so many severe problems to overcome in every new generation, and many new ideas have been proposed to solved them.
Figure 1. A brief history of transistor/LSI development. PCT: point-contact transistor.
The year 2022 was the 75th anniversary of the transistor invention, and I have written a number of articles related to the history of transistor inventions [2], [3], [4], [5], [6], [7]. In this article, I explain my experience of actually developing LSI products and their technologies at Toshiba during 26 years (1973–1999), using historical photographs and illustrations.
Toshiba used to be one of the world-leading companies for its seminal LSI technologies over the last quarter of the 20th century. Those technologies include the first CMOS microprocessors for electric calculators, by Y. Suzuki, in the early 1970s; the first automobile engine control 12-bit microprocessors, installed in the Lincoln Versailles in the late 1970s; one of the world’s first 1-Mb CMOS DRAMs, which dominated the global market in the late 1980s; and the invention of NAND flash memory, by F. Masuoka, at the end of the 1980s. Most of these great achievements were brought about not by the order of superiors but by the spontaneous ideas and enthusiasm of young engineers. At that time, the LSI industry was very young and rapidly growing, and every company was full of young engineers who started their career within several years of one another. During that period, Toshiba, as well as some other companies, had a corporate culture that allowed engineers to implement their ideas, spending a certain number of resources based on their own judgment, even if disapproved by their superiors, as long as they satisfactorily fulfilled their assigned responsibilities.
Figure 2 illustrates technology developments that I participated in at Toshiba. I joined Toshiba in 1973—immediately after the IC Laboratory, headed by Y. Takeishi, was founded in the R&D Center to enhance the development of silicon (Si) LSI technologies—and I retired from the Semiconductor Division in 1999. Before the foundation of the IC Laboratory, Toshiba was slightly behind in the development of mainstream LSI technologies, while advancing in the development of relatively special and unique IC/LSI technologies at that time, such as CMOS microprocessors and EPROMs.
Figure 2. The author’s LSI development experience at Toshiba. Al: aluminum; BPSG: borophosphosilicate glass; CVD: chemical vapor deposition; ECAD: electronic CAD; RTA: rapid thermal annealing; NiSi salicide: nickel mono-silicide self-aligned silicide; SiOxNy: silicon oxynitride.
My first job at Toshiba was the development of Toshiba’s first NMOS LSI technology with 1-kb SRAMs as a concept product, and I was appointed to lead a team consisting of several engineers and technicians, in 1974. NMOS LSI was the second generation of the LSI, after the first generation of the PMOS LSI, and the design rule shrank from 8 to 6 μm.
At that period, the structure of LSI was very simple compared with recent nano-CMOS, as demonstrated in Figure 3. The number of elements necessary for the chip was only five. There were only eight layers for the LSI, including the Si substrate, and the number of mask steps was only seven. They were 1) active area formation, 2) D (depletion)-type channel ion implantation, 3) direct contact between the poly-Si and Si substrate, 4) the poly-Si gate electrode, 5) the contact hole, 6) aluminum (Al) interconnects, and 7) the bonding pad opening.
Figure 3. A cross section of Toshiba’s first NMOS LSI. (a) Cross section, (b) magnified cross section, and (c) layers, materials, and elements used. SiO2: Si dioxide.
For the second-generation LSIs, ED logic circuits—a D-type n-MOSFET load with an E (enhancement)-type n-MOSFET driver [8]—were chosen by most of the companies, including us, because of their superior input-to-output transfer characteristics. Here, D type means negative Vth (threshold voltage) with normally-on operation, and E type means positive Vth with normally-off operation. Precise control of Vth by channel ion implantation had just started in the early 1970s, enabling the realization of E-type n-MOSFETs easily, which used to be difficult due to the existence of the positive Si/SiO2 interfacial charge. In our process, E-type channel ion (B) implantation was carried out for the entire wafer without a mask before the D-type implantation. Then, the D-type implantation (P) was performed with masking of the E-type MOSFET areas.
Figure 4 presents Toshiba’s 1-kb NMOS SRAMs: TMM311P and 312P [9]. The device parameters were as follows: gate length: 6 μm; gate SiO2 thickness: 100 nm; source/drain junction depth: 1.7–1.8 μm (${\rho}_{s}$ = 6 Ω/sq); Vth(E) = 0.9 V ± 0.2 V; Vth(D) = −3 V ± 0.6 V; Vth(Field) = 20 V; ${\rho}_{s}$ (poly-Si) = 20–40/Ω sq; cell size: 66 × 80 μm2; chip size: 3.16 × 3.72 mm2; access time: 300 ns; cycle time: 600 ns; power supply: 5 V; and power dissipation: 250 mW.
Figure 4. Toshiba 1-kb SRAMs. (a) Chip photograph. (b) Package and wafer photographs.
Prior to the NMOS 1-kb SRAMs, Toshiba produced a 256-b SRAM with an 8-μm Al gate PMOS LSI technology. The NMOS 1-kb SRAMs adopted Si gate technology. At Toshiba, Si gate technology was already introduced, by H. Iizuka and F. Masuoka, in 1972–1973, to the company’s stacked double-poly-Si gate structure for EEPROMs with a PMOS LSI technology [10]. My first experimental work at Toshiba in 1973 was to optimize the 6-μm poly-Si gate electrode etching. I adopted a 40-nm thermally grown SiO2 of poly-Si as the etching mask and determined the optimum composition of the etching solution for reducing the lateral etching to suppress the variation of the poly-Si gate length as HF 30 cc: HNO3 300 cc: CH3COOH: 450 cc, I2: 100 mg.
In the course of the development, a number of unexpected severe problems occurred, as described in the following.
Electron beam irradiation to an Al target to evaporate Al had been used for the Al film deposition. X-ray irradiation generated by the electron beam broke the atomic bonds at the Si/SiO2 interface and shifted Vth. Hydrogen annealing, called sinter, in forming gas (N2:H2 = 9:1) ambient at 450–500 °C, had been used to recover the Vth shift as well as to secure a good Al-to-Si contact. When starting the 6-μm NMOS technology development, there had often been short circuit failures between the drain and the substrate [Figure 5(c)]. This did not occur in the 8-μm process with the larger junction depth. At first, the cause was thought to be Al intrusion into the Si because of the silicide reaction. However, it was confirmed that Si atoms diffuse into the Al line at high temperature [Figure 5(a) and (d)], creating pits at the edge of the contact hole [Figure 5(b)] [11]. The immediate solution was to change the Al interconnect layout design to impede the Si diffusion, such as providing a slit against the diffusion path. Then, we introduced Al–Si (1%) as the evaporation target to saturate the Si concentration in the Al before the sinter process so as to suppress the Si diffusion.
Figure 5. The Al penetration (spike). (a) Si diffusion paths in Al, (b) contact hole after removing Al, (c) short circuit failure rate, and (d) Auger measurement of the Si concentration along the Al line.
Another big problem at the early stage of the development was nonuniform etching of SiO2 film [Figure 6(a)]. In the 1970s, most of the etching was conducted by liquid etchant. In addition to nonuniform etching, there were some strangely shaped residuals, such as polygon and dendritic shapes. The cause of the nonuniform etching could not be figured out for a few months despite intensive investigations day and night. One day, I observed that the center of a wafer was shining with a pearl color in the etchant and found that the nonuniform etching appeared only in the shiny area, under microscope inspection, after the etching. The shining was caused by room light reflection of the air bubbles on the wafer [Figure 6(b)], and this was confirmed because the shining disappeared by lifting up the wafer to the air and dipping it again. The polygon- and dendritic-shaped residuals were found to be caused by the precipitation of ammonium fluoride crystals in the bubbles. It was also confirmed that thicker resist film wafers easily attracted the bubbles [Figure 6(c)]. Because it was difficult to decrease the resist thickness considering the resist defect density, the immediate solution was to lift up the wafer to the air to break the bubbles and then dip it again into the etchant. Soon, we developed bubble prevention methods, such as dipping wafers into the surfactant solution before the etching and a wafer rotation system in the etchant to remove the bubbles.
Figure 6. Nonuniform etching. (a) A microphotograph after etching with SiO2 film. (b) The air bubble coverage during etching. (c) The air bubble wafer distribution versus the resist thickness. HF: hydrogen fluoride; NH4F: ammonium fluoride; H2O: water.
Figure 7 shows the 1-kb SRAM chip yield trend until the first commercial production. During that period, 21 test lots—typically consisting of 23 wafers per lot, with 140 chips per wafer—were fabricated for the examination and improvement of circuit performance, process conditions, and reliability characteristics. The mask design change/refinement was conducted six times. In the mid-1970s, a 40% chip yield at the die sort (wafer test) and a 70% package-assembled yield were assumed to be satisfactory levels for profitability. It took 18 months until the chip yield stabilized to about 40%. Then, microscope analysis of the SRAM failure bits was conducted for a typical wafer. The causes of 89 failures on a wafer were classified: photolithography pattern failures (including those caused by CVD practices): 32; CVD particles themselves: 12; scratches in the wafer peripheral: 13; and unknown: 8.
Figure 7. The NMOS 1-kb SRAM wafer yield trend. BT: bias temperature; LOCOS: local oxidation of Si; DAT: design approval test.
The existence of CVD particles on the patterns often led to fatal errors [Figure 8(a)], but this also caused pattern failures during the photolithography process, as detailed in Figure 8(b) and (c). The mask contact on the wafer crushed the particles, resulting in distortions of the resist and etched patterns. Furthermore, the debris of the crushed particles and the resist stuck to the mask, causing pattern failures for the next wafer photolithography. The solution was to increase the frequency of the clearing of CVD equipment and photolithography masks. However, the production line had to consider the tradeoff between the machine operation time and the chip yield. The particle-oriented failures were slightly mitigated by primitive methods, such as wafer wiping by cotton swabs and precrushing particles with a dummy glass mask, followed by wafer washing. The mask dirt problem was completely solved by the introduction of projection-type mask aligners, such as the Perkin–Elmer Micralign projection aligner, in the late 1970s.
Figure 8. CVD particles and photolithography pattern failure. (a) CVD particles. (b) The deformed resist and dirtied mask with crushed particles because of contact mask alignment. (c) The resist pattern failure caused by particles.
Thinning and disconnection of Al interconnects at the steps had caused reliability problems (Figure 9). Although phosphosilicate glass (PSG) reflow [12] had already been introduced by some other companies to smooth the steps, we chose borophosphosilicate (BPSG) reflow (Figure 9). Moisture absorption of PSG film with a high P concentration had sometimes caused an Al corrosion problem. While a P concentration of 2.7 × 1021/cm3 and 30-min anneal at 1,000 °C was necessary for the PSG reflow, a P concentration of 2.6 × 1020/cm3 with a B concentration of 2.2 × 1021/cm3 and 15-min anneal at 1,000 °C was found to be sufficient for the BPSG reflow. A one-order-of-magnitude smaller P concentration suppressed the hygroscopicity of the film and decreased the possibility of Al corrosion. We introduced BPSG reflow to the product in 1976, and probably this was the first in the world.
Figure 9. The (a) Al interconnects at the step and (b) step smoothing by BPSG reflow.
In September 1975, I/O leakage failure occurred at the bias temperature test when chips were assembled in plastic packages. This leakage was caused by the parasitic field MOSFET (field-MOS) turning on due to migrated charges from the plastic. This kind of field leakage had not happened for the previous 8-µm PMOS LSI technologies because of the higher field-MOS Vth—even without impurity doping—due to the positive Si/SiO2 interface charges. For NMOS LSI, the field-MOS Vth was determined by the B implantation used for setting the n-MOSFET Vth (0.9 V) and could not be independently raised to more than 10 V (Figure 10). To solve this problem, we were required to increase the field B concentration independently from that of the n-MOSFET channel. Because a 2-µm space margin was necessary for the mask alignment at that time, a self-alignment process of the field B implantation to the field oxide region was indispensable. This was possible only by introducing the self-aligning local oxidation of Si field isolation technique, invented by E. Kooi, in 1970 [13], and we raised the field-MOS Vth to 20 V to solve this problem.
Figure 10. The field leakage by migrated charges from plastic packaging.
After design approval tests, including various kinds of reliability examinations, 1-kb NMOS SRAM (TMM311, 312, and 313) commercial production started in 1976 (Figure 11). Eventually, deformed 60-mm-diameter wafers—which included cutting the upper and lower portions of the wafers so that the wafers set on the quartz boat fit in the 2-in wafer furnace tube—and a ×0.9-shrunk mask were used to increase the number of chips produced to 1.4 times in total.
Figure 11. The (a) mask alignment and (b) chip assembly on the production line in the mid-1970s at Toshiba.
The NMOS version (T3517A) of the 12-b TLCS-12 microprocessors were produced using our NMOS technology and installed in the engine control unit of the 1978 model Lincoln Versailles. The first 12-b microprocessors were originally fabricated with 8-μm Al gate PMOS technology, in 1973, but Ford requested improved performance through NMOS technology for use in commercial cars. The NMOS TLCS-12 was the world-first engine control microprocessor used for commercial cars.
In 1977, our group moved to the newly founded Semiconductor Device Engineering Laboratory, headed by Y. Takeishi, in the Semiconductor Division. I was appointed team leader of NMOS 64-kb DRAM technology development and worked with the circuit design team. The minimum linewidth was 3 µm, and this was the beginning of the VLSI era. After the successful test trial of the 4-µm 64-k DRAM chip design and fabrication, in 1977 [14], the first things to determine for the commercial device were the supply voltages, circuit specification, and chip size. Although 5 V was desirable from the 3-µm technology point of view, the supply voltages were initially determined as +10 and −5 V (the back gate power supply) by the circuit team’s request, considering the number of stored charges for the DRAM capacitor. However, the world standard became the 5-V-only power supply, in 1979, and we redesigned the circuit and the process technology [15]. The chip size (3.66 × 6.8 mm2) (Figure 12), decided considering the package requirement, happened to be one of the world’s smallest among the commercial 64-kb DRAMs. Because it was difficult to store all the complicated control circuits inside of the chip through the conventional process, we introduced new technologies, including stepper photolithography and “dry processes” such as source/drain ion implantation, non-isotropic reactive ion etching (RIE), and oxygen plasma resist ashing.
Figure 12. The 64-kb DRAM (TMM4164). (a) Chip photograph. (b) Package photograph. (c) Wafer photograph.
Toshiba purchased a kind of so-called beta machine, a Mann 4800 direct step on wafer (DSW) system, at the end of the 1970s. The 4800 DSW was the world’s first stepper conducting step-and-repeat light exposures on wafers for reduced pattern projection, using a 10:1 mask to enhance the pattern resolution. The stepper was quite a new concept, and we faced initial problems related to the new photolithography procedures as well as beta machine-related mechanical bugs. One of the biggest ones was the “common defect” problem. In that period, it was quite normal that there were one or two defects on a 1:1 mask, and this did not significantly affect the chip yield [Figure 13(a)]. However, in the case of the 10:1 mask, where only two chip patterns exist [Figure 13(b)], one or two defects decreased the yield by 50% or 100%, depending on the defect’s location [Figure 13(a)]. The mask quality was not significantly improved within a couple of years despite the mask makers’ effort, and inspection of the new masks was a huge burden of the device development engineers. Indeed, 44% of the new masks had defects in March 1980 [Figure 13(c) and (d)]. Eventually, automatic defect inspection machines were developed by several companies to reduce the human eye inspection labor. In 1981, Nikon steppers were introduced to 64-k DRAM development and later used for production.
Figure 13. The common stepper defect problem. (a) The projected mask defects for 1:1 and 10:1 masks. (b) The 10:1 Al interconnect pattern mask. (c) The mask failure list in March 1980. (d) The defects on a mask and resist patterns.
To integrate many components within a chip, suppression of the side etching of lines and side diffusion of impurities is important. We introduced RIE and source/drain ion implantation to integrate a large number of circuits components in a small chip. These technologies were called “dry process,” in comparison with the conventional “wet process” consisting of liquid etching and gas phase diffusion. We were one of the first to introduced the dry process to VLSI production.
As expected, there were several initial problems for the introduction of the dry process, such as resist film hardening due to ion bombardment and fluorocarbon film deposition as the reactive ion byproduct. The removal of those films was often not easy, even when introducing another dry process, resist ashing, for film removal using oxygen plasma. One of the biggest initial problems of RIE involved Si residues after the poly-Si RIE (Figure 14). The causes were soon found to be tiny etching-resistant areas made of some kind of oxides and/or fluorocarbons. Because of the small side etching nature of RIE, even a very tiny etching mask prevents the complete etching off of the poly-Si under it. It took more than a few months to completely solve the problem by enhancing the poly-Si surface cleaning process and tuning the RIE side etching conditions, resulting in the delay of the DRAM development schedule.
Figure 14. The poly-Si gate electrode RIE and residue.
Before the 64-kb DRAM generation, source/drain P (phosphorus) doping had been conducted by gas phase phosphorus oxychloride (POCl3) furnace diffusion. For the 64-kb DRAM, arsenic (As) ion implantation of 5 × 1015 cm−2 at 40 keV, by a Lintott high-current beam ion implanter, was adopted in experiments. A junction depth of <0.45 μm with a sheet resistance of <40Ω/sq was obtained. Ion implantation had been used since the early 1970s for the channel doping to adjust the Vth of MOSFETs, but the typical dose was only 1011–12 cm−2 with around 100 keV of acceleration energy. The three-orders-of-magnitude-larger ion dose and the As ions, being twice heavier than the P ions, were prior concerns for junction damage, but fortunately, no significant junction leakage was confirmed by the experiments.
At the end of July 1980, the development of 64-kb DRAM reached a stage where the majority of the chip failure modes was roughly one to 100 bit errors. However, the bit errors continued more than several months without any significant improvement, although it was suggested that the cause was memory capacitor gate oxide breakdown from the Poisson distribution of the bit errors. By inspecting the bit error memory cell [Figure 15(a)] by removing layers, holes were observed on the memory capacitor poly-Si electrode [Figure 15(b)]. After removing all the layers, small yellow round spots were found by staining the substrate with a chemical treatment [Figure 15(c) and (d)]. The yellow spots were found to be n+ Si pillars grown by the local melting of the n+ poly-Si gate electrode through gate oxide breakdown.
Figure 15. The bit error caused by PID. (a) A DRAM cell. (b) A hole on the poly-Si capacitor. (c) and (d) Yellow spots (the P-diffused region). (e) A Si pillar created by the gate oxide breakdown.
The gate oxide breakdown was caused by the accumulated charges at the poly-Si gate electrode by the ion bombardment during RIE and source/drain high-dose ion implantation (Figure 16). The problem was solved by tuning the ion bombardment process conditions. This was probably the world’s first observation of plasma-induced damage (PID) and was published as a late-news letter at an Electrochemical Society meeting in fall 1982 [16]. PID became a worldwide problem in the late 1980s.
Figure 16. The mechanism of plasma-induced damage.
CVD particles had been recognized as the major cause of yield degradation since the middle of the 1970s. For 64-kb DRAM production, various kinds of dusts (Figure 17) originating from wafer process and clean room environments were found to be a big problem causing significant yield degradation. Unfortunately, the clean room facility used for development and early production was not suitable to decrease the dust level. As a result, a huge number of resources were invested for the next generations of DRAMs to significantly improve the facility.
Figure 17. The various kinds of dusts on the 64-kb DRAM wafer. (a) A CVD particle. (b) A resist flake. (c) A poly-Si fragment.
Degradation of the charge retention due to various causes, such as heavy metals, carrier migration, and carrier generation by alpha particle radiation [17], were the concern. We introduced an intrinsic gettering wafer, in 1981, to suppress those degradations [18], [19]. The alpha particle-induced soft error was solved by coating the chip with a pure polyimide film.
Another big problem was the accuracy of the circuit design. At that time, the circuit simulation ability at Toshiba was not sufficient to simulate the NMOS enhancement-type MOSFET driver and enhancement MOSFET load (EE) logic circuit [20] used for the DRAM. The output level and switching time of the EE logic gate were quite dependent on the MOSFET geometry and characteristics and, thus, more complicated than those of CMOS logic. To reach the satisfactory level of the commercial DRAM specifications, 20 mask refinements, with each verification by device fabrications, were required. Through the development of the 64-kb DRAM, Toshiba established the VLSI production technologies—including stepper lithography and dry process—earlier than other companies, and learned about the importance of investing huge resources to the development and mass-production facility. Toshiba also recognized the difficulty of designing NMOS EE circuits. The earlier establishment of the VLSI production technology, and lessons learned from the development of 64-kb DRAM made a great success of Toshiba’s 1M bit CMOS DRAM that almost monopolized the world market in the late 1980s.
From 1983 to 1986, I was out of LSI device technology development. I was sent to the IC laboratory of Stanford University as a visiting scholar from 1983 to 1984, where I proposed on-chip measurement of small geometry MOSFET capacitances and their modeling. The Xerox Palo Alto Research Center was interested in my proposal and volunteered to fabricate samples. These were the first on-chip capacitance measurement circuits, and the resolution reached, unbelievably, down to atto (10−18) Farad [21]. The short channel effects (SCEs) of the MOSFET capacitances were discovered for the first time, and the cause of the SCEs was clarified to be the carrier velocity saturation [22], [23]. At Stanford, I also learned deeply about technology CAD and the mathematical theory of numerical solutions. After coming back from Stanford in November 1984, I was one of four designers ordered to design CMOS 1-Mb SRAM circuits [24]. I was also appointed in 1985 to lead a small team introducing an electronic CAD system for Toshiba memory design and chose Solomon Design Automation (SDA) Systems as the software and the Sun-2 engineering workstation as the hardware. Later, SDA was acquired by Cadence and became almost the world standard.
In October 1986, I was appointed the leader of three teams: 0.5-µm logic CMOS, 1.2/0.8-µm BiCMOS [25], and 0.8-µm mixed logic and SRAM technologies. In the late 1980s, BiCMOS was the highest-performance logic technology, used, for example, in Intel’s Pentium microprocessor. To realize a highly activated shallow impurity profile for the bipolar transistor, we introduced rapid thermal annealing (RTA), in 1989 [26], [27]. For the logic CMOS, hot carrier reliability degradation was one of the major concerns due to the electric field increase with the device size reduction. We conducted an intensive study of hot carrier-induced degradation [28], [29], [30]. Another new technology was the introduction of WSix polycide (stacked WSix and poly-Si) to decrease the poly-Si gate electrode resistance. The introduction of new materials was not easy, and there were problems of peeling of films caused by the thermal expansion difference (Figure 18) and impurity interdiffusion between n+ and p+ poly-Si regions through the WSix film [31].
Figure 18. The WSix film peeling. (a) Microphotograph. (b) SEM photograph.
In 1989, I moved to the ULSI Research Center, headed by Y. Takeishi, which had been founded as a corporate laboratory several years before, and I became the group manager of developing advanced logic CMOS and RF bipolar/BiCMOS technologies.
At the beginning of the 1990s, it was briefly imagined that the CMOS scaling limit could be about 0.1–0.07 µm [32] because of several reasons, such as difficulty in suppressing the leakage current, parasitic resistance increase, and Vth variation. But there was no proof and no deep understanding of device physics in the deep-sub-0.1 µm region. We conducted detailed analysis using Monte Carlo simulation, collaborating with the University of Bologna, from 1992 and published a new scaling scheme (or new roadmap) in 1993 (Figure 19) [33]. We predicted that a retrograde channel doping structure, such as one made by nondoped epitaxial growth, could operate at room temperature until gate length Lg = 25 nm and that, in case of double-gate MOSFETs [34], Lg could be scaled to below the 25-nm region. We also predicted the introduction of a high-k gate insulator from sub-50-nm generation. Later, Intel introduced high-k in 45-nm technology [35] and a FinFET (a vertical-type double-gate MOSFET) at 22 nm [36]. These facts proved that the predictions in our new scaling scheme were quite appropriate.
Figure 19. The CMOS scaling roadmap by Monte Carlo simulation published in 1993. (a) The MOSFET structures. (b) The scaling limit. (c) The roadmap for the supply voltage and gate oxide thickness.
To verify the operation of sub-50-nm MOSFETs, we fabricated 40-nm-Lg MOSFETs [37]. At that time, there was no stepper to realize the 40-nm photolithography and no shallow ion implanter for 10-nm junction depth with low resistivity. We selected a resist slimming technique [38] for the stepper photolithography and P (phosphorus) solid-state diffusion from the PSG gate sidewall by RTA [Figure 20(a) and (b)]. The realization of the 10-nm shallow junction with low resistance (6 kΩ/sq) [Figure 20(c)] was the key for the operation. It was confirmed that 40-nm-Lg n-MOSFETs operate with high performance at room temperature [Figure 20(d)]. The ${\sigma}$ (standard deviation) of Vth distribution in a wafer was as small as 0.05 V, even at a high Vd = 2 V. The demonstration of these experimental results broke the “red brick wall” of the scaling limit and kept the traditional scaling trend [39], [40], [41] (Figure 21).
Figure 20. The fabrication of 40-nm-gate-length n-MOSFETs. (a) Cross section. (b) Top view by scanning electron micrography (SEM). (c) Impurity depth profile measured by secondary ion mass spectrometry (SIMS). (d) Electrical characteristics.
Figure 21. The gate length scaling trend.
We used 3-nm-thick gate SiO2 for the fabrication of the 40-nm-Lg MOSFETs, due to concern about direct tunneling gate leakage (Ig) below 3 nm [Figure 22(a) and (b) [42]]. However, during our ultrathin Si oxynitride (SiOxNy) gate insulator MOSFET experiment in 1991, we had experienced a decrease in the ratio of Ig to the drain current (Id) with Lg reduction. We challenged the 1.5-nm-gate SiO2 MOSFET in 1994 [42], [43]. The 1.5-nm SiO2 film was grown by rapid thermal oxidation (RTO). The ultrathin SiO2 was quite uniform [Figure 23(a)] due to the strong oxidation of Si at the high RTO temperature at the early stage of the oxidation, preventing the local thinning (defect or variation) of the SiO2 film. The ${\sigma}$ of the SiO2 thickness in an entire wafer evaluated by MOS capacitor Ig was only 0.008 nm [44]. With decreasing Lg below 1 μm, Ig became ignorable compared with Id [Figure 23(b)]. We confirmed a world record transconductance value of 1,010 mS/mm at Vd = 1.5 V and Lg = 90 nm [42], [43].
Figure 22. The significant leakage current from the direct tunneling of the SiO2 gate oxide. (a) The direct tunneling leakage current mechanism. (b) The lg–Vg characteristics of 100 × 110-µm MOS capacitors.
Figure 23. The introduction of the direct tunneling of the SiO2 gate oxide. (a) A TEM photograph of 1.5-nm SiO2 grown by RTO. (b) The normal operation of a 1.5-nm-gate SiO2 MOSFET.
The successful results of our direct tunneling gate oxide MOSFETs with manufacturability and reliability [44] changed the international technology roadmap for semiconductors (ITRS) (Figure 24).
Figure 24. The (a) gate insulator thickness trends predicted by the ITRS and (b) real trends, with materials and thicknesses.
Demonstration of the 40-nm-gate-length MOSFETs and the 1.5-nm-thick-gate SiO2 MOSFETs as well as our new scaling scheme by Monte Carlo simulation had a great impact on the world semiconductor industry and enhanced the development of nano-CMOS technologies aggressively beyond the red brick wall of 0.1 µm.
Toward the nano-MOS generations, we introduced new materials ahead of other companies at the beginning of 1990s. One was the development of the SiOxNy gate insulator made by rapid thermal nitridation (RTN) for the suppression of B penetration (or diffusion), in 1990 [45]. The penetration occurs only for the p-type dopant of poly-Si gate and not for the n-type dopant. We demonstrated that several percent of the nitrogen atoms in the SiO2 film effectively suppresses the B penetration (Figure 25).
Figure 25. The suppression of B penetration by SiOxNy gate film made by RTN. (a) The B penetration. (b) The ld–Vg characteristics. (c) The N concentration profile by Auger spectroscopy. (d) The B concentration profile by mass spectrometry.
Traditionally titanium disilicide (TiSi2) had been used for salicide (self-aligned silicide for the source, gate, and drain [46], [47]) to reduce resistances. The silicidation reaction of the metal film does not take place on the field SiO2 and Si nitride (Si3N4) gate sidewall. Thus, the self-alignment of the silicide on Si regions can be conducted by removing the unreacted metal on the SiO2 and Si3N4 with an acid solution (Figure 26). There had been many problems, such as agglomeration of the silicide, bridging, and junction leakage. We chose nickel mono-silicide (NiSi) and developed NiSi salicide technology in 1991 (Figure 27) [48], [49]. The Ni silicidation mechanism that Ni diffuses into Si to form the silicide [as opposed to the Ti case (Figure 27(a)] completely solved the bridging and agglomeration problems [Figure 27(b)]. Furthermore, NiSi is suitable for shallow junctions because of less Si consumption during the silicidation because of the monosilicide. We were the first to develop NiSi salicide CMOS technologies, and they became the world standard from the end of 1990s until the late 2000s, when the high-k/metal gate stack was introduced.
Figure 26. The structure of salicide (self-aligning the silicide to the source/gate/drain) and its problems. Unreacted metal films on the gate sidewall and field oxides are removed by an acid solution.
Figure 27. The NiSi salicide. (a) The silicidation mechanism difference between TiSi2 and NiSi. (b) TEM photographs of the cross section and top of the TiSi2 and NiSi gate electrodes. (c) A SEM cross section of an NiSi salicide CMOS.
AC characteristics MOSFETs had not been suitable for RF applications, but we noticed that the RF performance of CMOS was expected to be greatly improved by scaling [50] and launched an RF CMOS development project, with collaboration from KU Leuven and ETH Zurich in the mid-1990s. We obtained a world record Si MOSFET fT value of 245 GHz by the end of the 1990s [51]. In 1998, our group moved to Microelectronics Engineering Laboratories, headed by Y. Unno, in the Semiconductor Division and published an RF CMOS roadmap, including the gate finger length optimization for fT, fmax, and noise figure for each generation [52]. From 1998, we started a collaboration with Erickson to extract the 150-nm RF CMOS parameters for circuit design, contributing to the development of Bluetooth [53]. Now, nano-CMOS has become the mainstream technology for RF front-end circuits for 4G and 5G applications.
LSI technology evolution from the 6-µm NMOS to the recent nano-CMOS was described based on my experience at Toshiba from 1973 to 1999. Unexpected problems often happened, resulting in severe yield degradation and delays in development schedules. It required many hours of hard work to survive the tough competition among strong rival semiconductor companies. However, the severe problems and competitions have been the source of innovations and evolutions. LSI technology development was a really exciting and rewarding job, having contributed to the realization of the superintelligent society.
The accomplishments were the results of the teamwork of all the members, and I would like to sincerely appreciate them, some of whose names appear as the coauthors of the references. Finally, I would like to express appreciation to my superiors at Toshiba: Y. Takeishi, M. Toyama, Y. Nishi, S. Horiuchi, S. Kohyama, N. Goto, Y. Unno, A. Kasami, and S. Komatsu, as well as Prof. T. Sugano (University of Tokyo) and R. Dutton (Stanford University) for their occasional precious advice guiding me to a professional engineer.
Hiroshi Iwai (h.iwai@ieee.org) has been a semiconductor device engineer working in the field of LSI and its technology development for 50 years, since 1973. He received his B.E. and Ph.D. degrees from the University of Tokyo. He joined Toshiba in 1973 and moved to the Tokyo Institute of Technology, Yokohama, Kanagawa, 226-8503, Japan, in 1999. He is now a professor emeritus at the Tokyo Institute of Technology and a vice dean and distinguished chair professor at National Yang Ming Chiao Tung University, Hsinchu City, 300093, Taiwan. He served as IEEE Electron Devices Society (EDS) president and IEEE Division I director. He is an EDS Eminent Lecturer, a Life Fellow of IEEE, and a committee member of IEEE International Roadmap for Devices and Systems.
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Digital Object Identifier 10.1109/MED.2023.3259978
Date of current version: 28 June 2023