Tak H. Ning
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The point-contact transistor was invented in 1947 by Bardeen and Brattain [1], and the sandwich-like BJT was invented by Shockley in 1948 [2]. While point-contact transistors were made and used briefly for a few years, it is Shockley’s sandwich-like device structure that is commonly referred to as a bipolar transistor.
The development of bipolar transistors in the early 1950s was to replace the vacuum tubes in data processing systems. At the beginning, transistors were used to replace vacuum tubes not for lower cost but for a much lower system failure rate, lower power dissipation, and a smaller system form factor.
At IBM, the development of bipolar transistor technology progressed rapidly in the mid-1950s, driven by the computer project named STRETCH [3]. Figure 1 shows schematically two of the advanced bipolar transistors developed at IBM for the company’s early computer systems [3]. To fabricate a transistor, we start with a lightly doped P-type substrate wafer. An n+ subcollector region is then formed in the P-type substrate by arsenic diffusion or by implantation followed by diffusion. A lightly doped n-type epitaxial layer is then grown. The thickness of the epitaxial layer is determined by the desired minimum separation between the bottom of the P-type intrinsic base region and the top of the n+ subcollector. Each transistor is isolated laterally by heavily doped P-type pockets and the P-type wafer substrate. The P-type base region is formed by boron diffusion or by boron implantation followed by diffusion. The subcollector layer is there to reduce collector resistance.
Figure 1. Bipolar transistors developed at IBM for use in its computer systems. (a) An earlier transistor structure without a recessed field oxide. (b) A more advanced transistor with a recessed field oxide, which was formed by masked thermal oxidation of recessed silicon regions.
The base width ${W}_{B}$ of a bipolar transistor is given by \[{W}_{B} = {x}_{jB}{-}{x}_{jE} \tag{1} \] where ${x}_{jB}$ is the base junction depth [measured from the silicon (Si) surface to the bottom of the P-type base region] and ${x}_{jE}$ is the emitter junction depth (measured from the Si surface to the bottom of the n+ emitter region). It is clear from (1) that ${x}_{jE}$ should be comparable to or smaller than ${W}_{B}$ to achieve transistors with controlled and reproducible thin base widths. Thus, one direction in the development of bipolar process technology in the early days was to reduce the emitter junction depth. By 1966, emitter junction depths as shallow as ${7}\,{\mu}{\text{ in}}$ ${(}{0.18}\,{\mu}{\text{m}}{)}$ were demonstrated at IBM [4].
Since the invention of the bipolar transistor, many bipolar logic circuits, e.g., DTL, TTL, ECL, merged-transistor logic (MTL), and integrated injection logic (I2L), have been used in products. Here, only ECL and MTL/I2L are briefly discussed.
Figure 2 presents a typical ECL circuit. It was invented by Yourke, in 1956 [5], and first used in IBM 7090 systems, announced in 1958. The transistor ${Q}_{4}$sets the switch current ${I}_{S}$. When the input ${V}_{\text{in}}$ turns on ${Q}_{1}$, ${I}_{S}$ flows through ${Q}_{1}$ and the load resistor ${R}_{L}$ connected to ${Q}_{1}$. When the input ${V}_{\text{in}}$ turns off ${Q}_{1}$, ${I}_{S}$ is switched from passing through ${Q}_{1}$ and its load resistor to passing through ${Q}_{2}$ and its load resistor. There is little transient current, and, hence, little switch noise, seen at the metal line connected to ${V}_{\text{CC}}$. The logic swing for an ECL circuit can be rather small, typically about 400 mV. ECL circuits were, and still are, the fastest logic circuits.
Figure 2. An ECL gate with fan-in = fan-out = 1 and an output capacitance loading of CL. Both the inverting and the noninverting outputs are shown.
In 1972, an exciting bipolar logic circuit was announced by Hart and Slob, of Philips [6], and Berger and Wiedmann, of IBM [7]. Hart and Slob called their circuit I2L, and Berger and Wiedmann called their circuit MTL. Figure 3 is a schematic of an I2L/MTL logic gate. It is by far the densest logic circuit. It uses minimum-size devices and requires one p-n-p per gate for current injection and one n-p-n per fan-out. Thus, the inverter in Figure 3 requires only four transistors. The same physical I2L/MTL can be operated at different injection currents, resulting in different circuit speeds, simply by varying the base–emitter bias voltage of the p-n-p ${V}_{\text{CC}}$ in Figure 3. In the 1970s, CMOS was still in its infancy. Thus, the advent of I2L/MTL generated a lot of excitement in the semiconductor industry. Many companies rushed into developing LSI chips using I2L/MTL.
Figure 3. An I2L/MTL gate with three fan-outs. Here, CL represents the load capacitance at the fan-out collector C1. When built using vertical transistor processes, the n-p-n transistors operate upside down, with the top n-regions acting as collectors and the bottom connected n-regions as a common emitter.
As ${x}_{jE}$ is reduced to achieve a small ${W}_{B}$, the base current increases because more and more holes can reach the metal emitter contact before recombining. As the base current increases, the base doping concentration is often reduced to maintain adequate current gain. A computer simulation study published in 1979 by Gaur [8] showed that the intrinsic base sheet resistance of a transistor having ${x}_{jE} = {30}\,{\text{nm}}$ increased to almost ${130}{k}{\Omega} / {□}$, causing the ${f}_{\max}$ of the transistor to drop to 6 GHz. The net is that the transistors in Figure 1 are not scalable.
By 1977, partly due to the recognition that bipolar transistors, as represented in Figure 1, were not scalable to thinner bases for better performance and partly due to the excitement generated by MOSFET and CMOS advances, research activities on Si bipolar technology, particularly in the United States, had fallen off drastically, as evidenced by a lack of publications on the subject. Of the 281 papers published in IEEE Transactions on Electron Devices in the 12 months between September 1976 and August 1977, only 19 were on Si bipolar. Of the 19 Si bipolar papers, only five were by U.S. authors. Major universities and research laboratories in the United States either never had research programs on Si bipolar to begin with or had phased them out by then.
Nonetheless, research activities on novel bipolar technology were active in Japan and Europe, mostly related to using heavily doped poly-Si as the doping source for forming and contacting the emitter and to using doped poly-Si to form resistors [7], [8], [9], [10], [11], [12], [13]. Figure 4 illustrates perhaps the most advanced bipolar device structure reported by February 1977. It uses arsenic-doped poly-Si as a diffusion source to form the emitter and contact the collector, and it uses the overhang in the poly-Si edge to shadow metal evaporation, achieving the self-alignment of the base contact to the emitter [13].
Figure 4. A bipolar transistor built using the so-called elevated electrode IC technology, reported at the 1977 International Solid-State Circuits Conference.
From the late 1950s to the mid-1990s, Si bipolar was the backbone technology for IBM’s data processing and computing systems. IBM had strong R&D programs on bipolar technology and circuits in its product development laboratories. In 1976, upper management decided that the IBM Research Division should establish a program on Si bipolar technology, with an objective of looking ahead and exploring the white space in bipolar technology not covered by the development laboratories. In January 1977, an exploratory bipolar devices and circuits group was formed at the IBM T.J. Watson Research Center; thus began the exciting years of Si bipolar technology exploration there. When the group was first formed, in January 1977, it consisted of six members: H.N. Yu was acting manager of the group, D.D. Tang focused on device design and modeling, P.M. Solomon focused on circuit design and modeling, T.H. Ning focused on device technology, G. Feth focused on circuit applications, and M.G. Smith focused on system applications. About a year later, R.D. Isaac, who had just obtained his Ph.D. degree from the University of Illinois Urbana-Champaign, joined the team and focused on process technology development. A bit later, S.K. Wiedmann, from IBM Boeblingen Laboratories, joined the team to focus on using the newly developed bipolar technology for logic and memory applications. Some of the key research directions taken by the team, and others at IBM, are described in the following.
It is evident from the device schematics in Figures 1 and 4 that the intrinsic device area of a vertical bipolar transistor, defined by the emitter area, is very small compared to the total area occupied by the transistor, which includes the areas occupied by contacts and isolation. A large parasitic device area also means large parasitic device and wire capacitances.
The transistor in Figure 4, with its metal base contact self-aligned to an emitter formed by diffusion from a doped poly-Si layer, has a significantly smaller total device area than the transistors in Figure 1. However, in our view, the fabrication process makes it difficult to optimize the doping profile of the intrinsic base and collector regions (the base and collector regions directly underneath the emitter opening). As a result, we decided to pursue the idea of first using boron-doped poly-Si to form the base contact and then self-align the emitter opening to the base poly-Si layer. By 1977, reactive ion etching (RIE) was already widely used in advanced technology development at IBM [14], [15]. We decided to use RIE to form an oxide spacer on the vertical etched surface of the base poly-Si to define the emitter opening. In this scheme, the intrinsic base and collector regions can be readily optimized by ion implantation through the emitter opening. The result is the self-aligned transistor in Figure 5, first reported at the 1980 International Electron Devices Meeting (IEDM) [16].
The IBM team did explore a self-alignment scheme similar to that in Figure 4. Indeed, for applications where the intrinsic device profile is not critical for circuit speed, it is a good alternative. The self-alignment scheme was employed to demonstrate the high-density and high-speed I2L/MTL circuit, described schematically in Figure 6, at the 1979 IEDM [17]. Using ${2.5}{-} {\mu}{\text{m}}$ design rules, an I2L/MTL gate with a fan-out of three showed delays as small as 0.8 ns [18].
Figure 6. Self-aligned I2L/MTL circuits using metal base contacts self-aligned to the emitter. The emitter was formed by diffusion from a heavily doped poly-Si layer (the dark layer in the drawing). The metal contact to the base is separated from the emitter by an oxide sidewall spacer [17], [18]. (a) The cross-sectional schematic of the device structure, for a circuit with three fan-outs. (b) The corresponding circuit schematic.
It is obvious from the schematics in Figures 1 and 4 that the junction isolation scheme, i.e., the large and deep vertical p-pockets, takes up a lot of area and has correspondingly large collector–substrate capacitance. The concept of using deep trench isolation to replace p-pocket isolation was evolving at the time at IBM [19], [20], so we decided to pursue deep trench isolation.
At IBM, the poly-Si emitter was discovered unexpectedly. A series of experiments, illustrated in Figure 7, was designed to study the differences among implanted and diffused shallow emitters contacted by silicide, aluminum, and arsenic-doped poly-Si. To avoid any ambiguity, all three kinds of emitter contacts were designed to be on the same wafers. The masking procedure was such that one of the devices [the device in Figure 7(b)] received no emitter implant at all but had the n+ poly-Si layer formed directly on the P-type base layer. There was no “diffusion from the doped poly-Si” thermal cycle. This device was not expected to work since the conventional wisdom at the time suggested that the poly-Si contact would behave like an ohmic contact, due to recombination at the interface of the arsenic-doped poly-Si and the P-type single-crystal Si. However, we found, to our great surprise, that the device not only worked properly but also showed the largest current gain of the four devices (see Table 1). We published the data from the planned experiments [21], [22] but kept the poly-Si emitter data proprietary.
Figure 7. (a) The emitter contact experiments in which (b) the poly-Si emitter was discovered.
Table 1. The typical measured current gains of the bipolar transistors sketched in Figure 7, for a base sheet resistance value of about 7 KΩ/4.
The physics and technology of the poly-Si emitter was the subject of intense studies in universities and industrial laboratories worldwide in the 1980s. Most of the papers up to 1989 were collected in one publication [23]. It is a good reference and contains an excellent introduction to the theoretical and experimental aspects of poly-Si emitter bipolar transistors.
In operation, the speed of a vertical bipolar transistor increases with the collector current, reaching a peak, and then falls off rapidly as the collector current is increased further. The falloff of the speed at high collector currents is due to base widening, or the Kirk effect [24]. It occurs when the n-type collector doping concentration is not high enough to support the electron current emitted from the emitter and arriving at the collector. In other words, the maximum speed of a vertical bipolar transistor is not determined by its base width but by its collector doping concentration. This important point is central to a new procedure for optimizing the design of the intrinsic base and collector of a bipolar transistor in 1979 [25]. A theory for scaling this optimally designed transistor to smaller dimensions was also published the same year [26]. Several constraints and requirements are imposed in scaling the transistor. These constraints and requirements for ECL circuits are listed in Table 2. Here, ${V}$ is the power supply voltage, ${\Delta}{V}$ is the logic swing, ${C}_{\text{DE}}$ is the emitter diffusion capacitance, and ${C}_{\text{dBC}}$ is the base collector junction depletion layer capacitance. The power supply voltage remains constant in bipolar scaling because the turn-on voltage of a p-n diode is relatively independent of its area. Reducing the diode area by ${10}\,{\times}$ increases its turn-on voltage by only 60 mV. By following these constraints and requirements, the scaling theory suggests that the delay of an ECL circuit is reduced by ${\alpha}$ when the emitter area is reduced by ${\alpha}^{2}$ and the circuit switch current density is increased by ${1} / {\alpha}^{2}$. That is, an ECL circuit implemented in an optimally designed bipolar technology scales with speed improvement but without a reduction in power dissipation. In other words, just two years after the start of the bipolar research program, the IBM team knew that power dissipation issues would eventually limit the scaling of ECL circuits.
Table 2. The constraints and requirements in ECL scaling [26].
The device design methodology and scaling theory serve as a valuable guide for designing the intrinsic base and collector regions. To tailor the collector doping concentration directly under the emitter only, the pedestal collector concept [27] was used. For our self-aligned transistor structure (see Figure 5), the pedestal collector was formed by high-energy ion implantation when the emitter opening was defined. In the literature, this implanted pedestal collector is often referred to as a self-aligned implanted collector.
By 1977, driven by a ${1}{-} {\mu}{\text{m}}$ n-channel MOSFET VLSI research program, electron beam lithography was available at IBM Research [28]. So, we decided to pursue integration of the self-aligned bipolar transistor, shown in Figure 5, and deep trench isolation with a recessed field oxide, using ${1.25}{\kern0.0em-} {\mu}{\text{m}}$ electron beam lithography. The final device structure is displayed schematically in Figure 8. The first successful experiment, showing ECL gates with a delay of 114 ps at a power dissipation of 4.9 mW, was reported at the 1982 International Solid-State Circuits Conference [29]. At the time, we decided to keep the details of the poly-Si emitter and the pedestal collector proprietary and, hence, did not highlight them in publications.
Figure 8. A deep trench-isolated double-poly-Si self-aligned n-p-n transistor with a pedestal collector.
In the 1980s, many research papers on using poly-Si to form self-aligned bipolar transistors with a small base–collector junction area were published. Among them, the sidewall base contact structure [30] and the superself-aligned transistor structure [31] have the potential of a smaller base–collector junction area than the structure in Figure 8.
At IBM Research, the first successful SiGe base transistor was reported, in 1987, using a molecular beam epitaxy process to form the SiGe layer [32]. A bit later, after Meyerson demonstrated an ultrahigh-vacuum–CVD process for forming SiGe layers with controlled Ge distribution [33], researchers at IBM started to explore replacing the implanted Si base with an in situ doped SiGe base formed by the new CVD process. They reported the successful integration of a poly-Si emitter with a graded-Ge SiGe base formed by the new CVD process in 1989 [34], [35].
Compared to Si base transistors, graded-Ge SiGe base transistors offer greatly improved device characteristics for RF and analog applications. Figure 9 is a plot of the relative improvement in current gain, Early voltage, and base transit time for a linearly graded SiGe base transistor compared to an Si base transistor of the same base doping profile, plotted as a function of the maximum bandgap lowering at the collector end. It shows a graded-Ge SiGe base transistor is much superior to an Si base transistor by these comparisons.
Figure 9. Relative improvements of a linearly graded-Ge SiGe base transistor compared to an Si base transistor.
The bipolar transistors we have discussed so far are vertical transistors, where the collector current flow is vertical, i.e., perpendicular to the Si surface. From the early 1990s to the early 2010s, IBM had an SOI CMOS program. As the CMOS gate length was scaled down to about 50 nm, we adapted the SOI CMOS process to make thin-base complementary symmetric lateral bipolar transistors where the collector current flow is lateral, i.e., parallel to the Si surface. The integration of lateral n-p-n and p-n-p transistors on the same chip, as detailed schematically in Figure 10, was first reported at the 2011 IEDM [36]. Unlike a vertical transistor, a symmetric lateral transistor does not have the Kirk effect (the base widening into the collector). As a result, a symmetric lateral transistor can be operated at much higher current densities than a vertical transistor, without performance degradation.
Figure 10. The integration of n-p-n and p-n-p symmetric lateral bipolar transistors on SOI.
The advent of the poly-Si emitter, together with the self-alignment and deep trench isolation schemes, enabled vertical bipolar transistors to achieve ultrathin base widths and reduced the device area and capacitance to values consistent with the fabrication processes employed. The pedestal collector scheme enabled the transistor collector to be optimized to its intended circuit application. In 1990, IBM announced a family of computer systems, the ES/9000 mainframe series, built using this advanced bipolar transistor together with four planarized metal layers. Figure 11 is a schematic of this bipolar technology [37].
Figure 11. The bipolar transistor and metallization used in IBM’s ES/9000 systems.
The IBM ES/9000 was the most powerful family of mainframes ever produced using bipolar technology, but it was also the last generation of mainframes produced using bipolar technology. IBM switched from bipolar to CMOS for its S/390 (G3) processor in 1996, and Intel switched to all CMOS for its Pentium processors in the mid-1990s.
Many talks have been presented and papers written about why CMOS has replaced bipolar as the backbone of high-performance computer systems. In my opinion, the fundamental reason has to do with the fact that a CMOS circuit has negligible standby power dissipation, while a bipolar ECL circuit dissipates the same power in standby and during switching, as explained in the “Bipolar Transistor Design, Scaling, and Pedestal Collector” section. Thus, a digital system designer can put lots of “standby” CMOS circuits on a chip and in the system, with little additional cost associated with the chip and system cooling. The same design option is simply not available for systems built using vertical bipolar circuits.
However, every technology has its limits, and CMOS is no exception. For a long time, a common practice in designing a scaled CMOS device was to allow its off current to increase from one generation to the next, by reducing the device threshold voltage, to increase its on current to achieve the targeted performance of the scaled device. CMOS for high-performance computing started its march toward the scaling wall when its off current was capped at ${100}{\text{ nA}} / {\mu}{\text{m}}$, beginning with the 65-nm node. Capping the off current in designing scaled CMOS devices severely limits the speed (clock frequency) of microprocessors. Today, the maximum speed of high-performance CMOS microprocessors is about 5 GHz [38], practically the same as those in 2009.
SiGe base vertical bipolar transistors missed the “bipolar for high-performance computing” era completely but arrived just in time for the takeoff of the “personal wireless communication era.” As indicated in Figure 9, vertical SiGe base bipolar transistors are far superior than vertical Si base bipolar transistors in terms of current gain, Early voltage, and base transit time. SiGe base bipolar has been used in Wi-Fi power amplifiers for more than 10 years. Today, BiCMOS based on the integration of SiGe base bipolar and CMOS, with an ${f}_{\max}$ of 400 GHz, is finding increasing applications in optical and wireless networks, satellite communications, and infrastructures.
The doping concentration of the pedestal collector region of a vertical bipolar transistor (see Figure 8) is significantly lower than the base doping concentration. As a result, the maximum speed of a vertical bipolar transistor, including the SiGe base bipolar transistor, is limited by the Kirk effect, which sets in when the transistor collector current density is larger than can be supported by the collector doping concentration. When the Kirk effect becomes significant, the speed of a vertical transistor decreases, instead of increasing, as the collector current is increased further. Therefore, it will be a challenge to increase the ${f}_{\max}$ of vertical SiGe base bipolar transistors toward 1 THz.
Going forward, the symmetric lateral transistors on SOI (see Figure 10) offer intriguing opportunities. Compared to CMOS, they have a much higher drive current per unit “channel width” [39], and they do not have the Kirk effect. Computer simulations suggest that a lateral transistor could have an ${f}_{\max}$ of 1 THz or larger when operated at high collector currents [40]. And, with emitter/collector symmetry, lateral transistors have the same speed with emitter–base switching and with collector–base switching. ECL gates and I2L/MTL gates implemented in symmetrical lateral transistors should have comparable minimum gate delays. One can imagine designing a processor chip containing many identical cores in symmetric lateral bipolar technology, using I2L/MTL circuits and CMOS-like complementary bipolar circuits, with most cores running at a base speed in ultralow-power mode, some cores running at 10 to ${100}\,{\times}$ the base speed and dissipating 10 to ${100}\,{\times}$ higher power per core, and a couple of cores operating as accelerators running at ${1,000}\,{\times}$ the speed and dissipating ${1,000}\,{\times}$ the power of the ultralow-power cores [40], [41]. Such a “performance-on-demand” system design concept is beyond the reach of CMOS. However, just like any new device technology, it will take one or more compelling applications and a sound business case to drive the investments needed to take symmetric lateral bipolar transistors on SOI from concept and feasibility to volume manufacturing.
Tak H. Ning (tak.h.ning1@gmail.com) is a retired IBM fellow and a Life Fellow of IEEE.
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Digital Object Identifier 10.1109/MED.2023.3257127
Date of current version: 28 June 2023