Haifeng Lyu, Yuchen Cao, Kenle Chen
PHOTO COURTESY OF HAIFENG LYU
The prestigious High-Efficiency Power Amplifier (HEPA) Student Design Competition (SDC) has been held annually for 17 years. In 2021, the competition was held virtually, live streamed from Keysight Technology’s Microwave Measurements Lab on 15 October 2021. The contest, organized by the IEEE Microwave Theory and Technology Society in collaboration with Keysight Technology, provides an opportunity for students from around the world to compete in the design of power amplifiers (PAs) with high linearity and high efficiency over a specified instantaneous bandwidth. The competition requirements for the 2021 winning design were as follows [1]:
Advanced PA architectures, such as Doherty [2], [3], [4], [5]; out-phasing [6]; and hybrid asymmetrical load modulated balanced amplifier (LMBA) [7], [8], are all good choices for the competition due to their ability to maintain high linear efficiency over a large dynamic power range. As with last year’s championship design [9], the Doherty PA (DPA) architecture was again selected as the solution for the competition, not only in light of the required third-order intermodulation (IM3) but also with an eye to mitigating amplitude-to-amplitude (AM–AM) and amplitude-to-phase (AM–PM) distortion in the load modulation region.
Growing data rates and increasingly complex modulation schemes are prompting stringent requirements for the output signal fidelity of RF transmitters in modern wireless communications. As the most popular load modulation PA architecture, highly efficient and linear DPAs are in great demand. From a harmonic cancelation perspective, providing short termination of the second harmonic of the DPA to reduce the IM3 has been studied in several articles [10], [11], [12]. At the same time, due to the load modulation and Miller effect between the main/auxiliary cells in a DPA, AM–AM and AM–PM distortion are more challenging than with a single-ended PA. Various compensation combining network methods have been proposed to reduce the phase variation of the output stage of the DPA, such as in [13], [14], and [15].
Similarly, a flat and expanded AM–AM profile is essential to deliver the highest possible PAE at the maximum linear power. Like the fact that the PA’s output load is modulated to boost the back-off efficiency, the optimal source impedance is also varied dynamically with the increasing input power. This power-dependent behavior has a significant influence on the gain (AM–AM) behavior. The AM–AM correction is basically realized empirically by a slight mismatch in the input matching or by adaptively tuning for the gate biasing [16]. Despite some research into the impact of the input baseband and harmonic terminations on the AM–AM profile, there has not yet been a sophisticated design methodology that considers both the overall AM–AM expansion and AM–PM improvement, which has resulted in a tested prototype. Therefore, the aim of this year’s winning SDC design was to improve the AM–AM and AM–PM of the DPA while achieving a good PAE with the required C/I ratio.
The classical DPA’s output combiner can be modeled as a three-port network with two in phase (I) and quadrature (Q) current sources (i.e., the main and auxiliary PAs) and a common load, as shown in Figure 1(a). The current and voltage relationship of all of the ports of the combiner can be expressed as an admittance matrix. Although the backoff efficiency can be boosted with a traditional combiner, linearity degradation due to the real transistor parasitics remains an issue.
Figure 1. The (a) classical and (b) proposed quadrature-coupler-based linear DPA.
Recently, a quadrature coupler has been used as a Doherty combiner to improve the linearity/bandwidth [17], [18], [19]. In particular, the three-port DPA combiner is synthesized to a four-port combiner by inserting two quarter-wave transmission lines (TLs) symmetrical to the previous TLs with the same characteristic impedance to form a coupler combiner, as shown in Figure 1(b). By terminating the isolation port to ground, this four-port combiner is equivalent to a classical DPA combiner. Further, if the short-circuited port is replaced by a small reactance (capacitive or inductive) load, the load modulation characteristic of the main/auxiliary PAs can be collectively modulated by the current source and the capacitive termination. As with the LMBA architecture, the injection from the isolation port at the third path tuning offers an expanded design space for the overall load-line, AM–AM, and AM–PM behaviors. From the matrix in Figure 1(b), the output voltage ${V}_{0}$ can be expressed as \[{V}_{O} = \frac{{-}\sqrt{2}{I}_{M}{-}{j}\sqrt{2}{xI}_{A}}{{jx} + {1}}{Z}_{0} \tag{1} \] which represents the overall AM–PM and AM–AM variation over the power sweep. For $\left({{x} = {0}}\right)$ in (1), which corresponds to the classical DPA combiner, the AM–-PM distortion is determined by the main PA’s parasitics (e.g., ${C}_{\text{DS}}$), leading to a phase deviation from the ideal case. However, the reactive loading $\left({\pm{jx}}\right)$ can reshape the output voltage profile in (1), thus changing the overall AM–PM when the auxiliary PA turns on. This can be utilized to generate a predefined AM-PM to counteract the distortion of the main PA. To investigate the phase compensation generated by this reactive loading, the DPA performance with a four-port matrix was mathematically derived in terms of the linearity (AM–AM and AM–PM) and efficiency. A piecewise ideal class B model with the harmonics short-terminated was applied to represent the transistors as linear voltage-controlled current sources.
Using the ABCD matrix together with the fundamental and dc voltage and current expressions, the phase and amplitude distortions under different values of reactive loading can be calculated, as plotted in Figure 2. From Figure 2(a), it is clear that a larger reactive load brings about a larger phase distortion. Considering that the main contribution of the AM–PM is the power-dependent ${C}_{\text{DS}}$, different $\left|{x}\right|$ loads can be implemented for different power transistors to compensate for the phase distortion. As for the amplitude distortion in Figure 2(b), only 0.2 dB of AM–AM compression is generated when producing a 10° AM–PM profile, and this compression can be reshaped through gain expansion design at the input side, which will be described later. The voltage magnitude ${V}_{M}$ of the main PA due to the proposed combiner is less than the dc supply rail, which guarantees the linearity. Figure 3 shows the calculated drain efficiency versus the normalized input power; a ${>}{70}{\%}$ back-off efficiency can still be maintained for $\left|{x}\right| = {0}{.}{2}{.}$ Note that a higher peak linear PAE is more rewarding in terms of the competition.
Figure 2. The (a) AM–PM and (b) AM–AM of the proposed linear DPA.
Figure 3. The efficiency profile of the proposed DPA.
To further explain the theory, an emulated circuit model of the proposed DPA is developed in [18]. Bare-die transistor models are de-embedded by incorporating static negative parasitic components. The AM–PM responses are simulated with different reactive loading values. The DPA with a short-circuited loading impedance [the black curve in Figure 4(a)] can suffer from large AM–PM distortion, especially during load modulation. Nevertheless, a capacitive loading of ${5}{pF}\left({{x} = {-}{0}{.}{2}}\right)$can largely linearize the AM–PM [the red curve in Figure 4(a)], leading to a flat AM–PM profile.
Figure 4. The (a) emulation model with AM–PM profiles and (b) source impedance selection for the gain profiles. MN: matching network.
After the AM–PM was designed, the improvement in AM–AM distortion was studied. The magnitude of ${V}_{M}$ is maintained as a constant over the load modulation region with the increased input power, which leads to the gain compression of the DPA. Adaptive gate biasing together with an uneven power splitter is the most widely employed way to modify the load modulation behavior to provide a sweet spot for the peak PAE. In this article, we would like to explore the method of power-dependent input matching to set up a gain expansion that not only maintains the IM3 at a lower backoff region but also engenders a sharper roll-off during gain compression, which extends the linear region with higher efficiency.
To explain the effect of input impedance selection on the AM–AM response, the emulation model in Figure 4(a) is revisited, and the capacitive loading at the output isolation port is maintained at 5 pF to achieve the best AM–PM. The source impedance of the main amplifier is kept at ${Z}_{\text{S}1},$ which is chosen based on the source pull for the optimal PAE contour. Since the class C peaking cell has more contribution around the peak power, three sample source impedances (${Z}_{\text{S}1},\,{Z}_{\text{S}2},$ and ${Z}_{\text{S}3}$) are evaluated with corresponding AM–AM profiles in Figure 4(b) for the peaking amplifier. The ${Z}_{\text{S}2}$ and ${Z}_{\text{S}3}$ are on the same PAE contour with different impedance values. A gain expansion of the overall DPA is clearly seen by setting the peaking device’s source impedance to ${Z}_{\text{S}3},$ while the other two impedance points both lead to a gain compression. Therefore, we can take advantage of this characteristic to carefully set the gain profile to improve the AM–AM and achieve better PAE.
To verify the theory proposed in the previous section, commercial gallium nitride high-electron mobility transistors (CGH40006P from Wolfspeed) are used to manufacture the DPA on a 20-mil-thick Rogers 5880 substrate with a dielectric constant of 2.2.
In this design, the drain supply voltage is set to 26 V, and the gate bias is ${V}_{\text{GS}1} = {-}{2}{.}{43}{V},\,{V}_{\text{GS}2} = {-}{3}{.}{65}{V}$for the tradeoff between the IM3 and power generation. The input impedance for the main amplifier is designed based on a source-pull simulation for the best achievable PAE, while a modification is implemented for the auxiliary path to fit the power-dependent source impedance trajectories with increasing input power.
The complete schematic circuit is shown in Figure 5, where the equivalent parasitic network is absorbed into the output matching network with the aim of enhancing the linearity. A 3-dB coupler at 3.5-GHz is designed with the AM–PM compensation isolation reactive loading at 3.5 pF through overall optimization. The input matching networks of the main and auxiliary PAs are designed with similar structures but with slight source impedance differences to provide the optimized AM–AM impedance with input power variation. Specifically, the main PA is efficiency optimized in the back-off region before the auxiliary PA turns on. A less resistive source impedance is applied for the auxiliary PA to obtain a gain expansion in the high-power region. To stabilize the normal quiescent point of the PA, a series of bypass capacitors to decouple the dc from the RF is implemented in the bias circuitry to resonate out the input and output baseband impedance effects.
Figure 5. The schematic of the DPA
In the one-tone simulation, a gain expansion at Doherty power regions is realized, as shown in Figure 6, with an extended range to boost the PAE. Meanwhile, a ${<}{5}$ AM–PM is maintained up to the output 1-dB compression (P1dB) region with a 62.1% PAE achieved. Further, a tone spacing of 20 MHz of the two-tone simulation is performed at 3.5 GHz to evaluate the DPA IM3 using harmonic balance simulation. An IM3 of lower than –35 dBc is maintained at the lower power region in the two-tone simulation to mimic the competition test environment [the dashed line in Figure 7(a)]. A 62.1% PAE is recorded at 24-dBm (21-dBm for each tone) input power, and a >13-dB gain is achieved up to >37-dBm output power delivered before hard compression.
Figure 6. The simulation results of the DPA.
Figure 7. The two-tone simulated and measured results for (a) IM3 and (b)PAE and gain.
A photograph of the fabricated DPA is shown in Figure 8. The IM3 with C/I ratio is monitored at the output end with the same setup as in [9]. The IMD3 versus the output power performance is plotted in Figure 7. The optimal gate-biasing voltage for the main and auxiliary PAs is set to a quiescent current of 0.195 A. The drain bias for the main and auxiliary PAs is 26 V due to the equal-cell DPA design. A voltage divider is designed to supply the gate bias voltages for a deep class AB mode of the main cell to obtain an IM3 sweet spot at the high-power region, while a class C mode is biased for the auxiliary cell to combine the gain compression and expansion stages to improve the linearity. The measured PAE, IM3, and gain versus output power in the two-tone evaluation are shown in Figure 7 (solid lines). At the rated 24-dBm input power, a gain of 13 dB is obtained, with the two-tone PAE reaching 57.2% at 3.485 GHz when the first C/I = 30 dB is met, which corresponds to an FOM of 78.1.
Figure 8. The top view of the fabricated DPA. IMN: input matching network; RF: radio frequency.
An LTE signal with 9.5-dB PAPR and 20-MHz modulation bandwidth was further performed. As shown in Figure 9(a), the designed DPA presents a 48.7% average efficiency, –37.5-dBc APCR, and 2.3% error vector magnitude for 64 quadrature-amplitude modulation at an average power of 32.1 dBm. A wideband 5G–New Radio 80-MHz modulated signal is characterized at the center frequency as well. The proposed DPA achieves an average efficiency of 42.1%, with <32.9-dBc Adjacent Channel Power Ratio (ACPR) around the 32-dBm average output power without Digital Pre-Distortion (DPD) applied [Figure 9(b)].
Figure 9. The modulation measurement at 3.485 GHz with (a) LTE and (b) a 5G NR signal.
This article describes the winning design of the 2021 HEPA SDC in terms of the theory, realistic design, prototype implementation, and measurement. A Doherty combiner is designed for an overall AM–PM mitigation together with implementation of power-dependent input impedance to improve the AM–AM distortion by gain expansion. The team’s PA achieved an FOM of 78.1 to win the live streamed competition.
[1] “IMS2020 student design competition rules,” IEEE Microw. Theory Technol. Soc., 2021. [Online] . Available: https://mtt.org/hepa_student_design_competition
[2] C. Musolff, M. Kamper, Z. Abou-Chahine, and G. Fischer, “A linear and efficient Doherty PA at 5 GHz,” IEEE Microw Mag., vol. 16, no. 1, pp. 89–93, 2015, doi: 10.1109/MMM.2014.2367862.
[3] X. Y. Zhou, W. S. Chan, D. Ho, and S. Y. Zheng, “Loading the third harmonic: A linear and efficient post-matching Doherty PA,” IEEE Microw. Mag., vol. 19, no. 1, pp. 99–105, Jan./Feb. 2018, doi: 10.1109/MMM.2017.2759669.
[4] T. Qi, S. He, F. You, W. Shi, X. Tang, and Y. Pan, “Canceling intermodulation products: A high-efficiency and linear-asymmetric Doherty PA,” IEEE Microw. Mag., vol. 20, no. 1, pp. 98–103, Jan. 2019, doi: 10.1109/MMM.2018.2875613.
[5] P. Yadav, “Optimizing the Doherty amplifier: Design of a 3-GHz GaN Doherty amplifier achieving 60% efficiency,” IEEE Microw. Mag., vol. 21, no. 2, pp. 88–95, Feb. 2020, doi: 10.1109/MMM.2019.2953348.
[6] C. Liang, P. Roblin, Y. Hahn, Z. Popovic, and H. Chang, “Novel outphasing power amplifiers designed with an analytic generalized Doherty–Chireix continuum theory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 8, pp. 2935–2948, Aug. 2019, doi: 10.1109/TCSI.2019.2910471.
[7] D. J. Shepphard, J. Powell, and S. C. Cripps, “An efficient broadband reconfigurable power amplifier using active load modulation,” IEEE Microw. Wireless Compon. Lett., vol. 26, no. 6, pp. 443–445, Jun. 2016, doi: 10.1109/LMWC.2016.2559503.
[8] Y. Cao, H. Lyu, and K. Chen, “Asymmetrical load modulated balanced amplifier with continuum of modulation ratio and dual-octave bandwidth,” IEEE Trans. Microw. Theory Techn., vol. 69, no. 1, pp. 682–696, Jan. 2021, doi: 10.1109/TMTT.2020.3014616.
[9] H. Lyu, Y. Cao, and K. Chen, “Linearity-enhanced and highly efficient Doherty power amplifier: 16th high efficiency power amplifier student design competition,” IEEE Microw. Mag., vol. 22, no. 10, pp. 62–69, Oct. 2021, doi: 10.1109/MMM.2021.3095979.
[10] D. Jung, H. Zhao, and H. Wang, “A CMOS highly linear Doherty power amplifier with multigated transistors,” IEEE Trans. Microw. Theory Techn., vol. 67, no. 5, pp. 1883–1891, May 2019, doi: 10.1109/TMTT.2019.2899596.
[11] S. Kang, D. Baek, and S. Hong, “A 5-GHz WLAN RF CMOS power amplifier with a parallel-cascoded configuration and an active feedback linearizer,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 9, pp. 3230–3244, Sep. 2017, doi: 10.1109/TMTT.2017.2691766.
[12] C. Fager, J. C. Pedro, N. B. D. Carvalho, H. Zirath, F. Fortes, and M. J. Rosario, “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 24–34, Jan. 2004, doi: 10.1109/JSSC.2003.820860.
[13] W. Hallberg, M. Özen, D. Gustafsson, K. Buisman, and C. Fager, “A Doherty power amplifier design method for improved efficiency and linearity,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 12, pp. 4491–4504, Dec. 2016, doi: 10.1109/TMTT.2016.2617882.
[14] G. Lv, W. Chen, Y. Zhang, N. Chen, F. M. Ghannouchi, and Z. Feng, “A highly linear GaN MMIC Doherty power amplifier based on phase mismatch induced AM-PM compensation,” IEEE Trans. Microw. Theory Techn., vol. 70, no. 2, pp. 1334–1348, Feb. 2022, doi: 10.1109/TMTT.2021.3131199.
[15] X. Fang, A. Chung, and S. Boumaiza, “Linearity-enhanced Doherty power amplifier using output combining network with predefined AM–PM characteristics,” IEEE Trans. Microw. Theory Techn., vol. 67, no. 1, pp. 195–204, Jan. 2019, doi: 10.1109/TMTT.2018.2870830.
[16] R. Giofré, L. Piazzon, P. Colantonio, and F. Giannini, “A Doherty architecture with high feasibility and defined bandwidth behavior,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 9, pp. 3308–3317, Sep. 2013, doi: 10.1109/TMTT.2013.2274432.
[17] H. Lyu and K. Chen, “Balanced-to-Doherty mode-reconfigurable power amplifier with high efficiency and linearity against load mismatch,” IEEE Trans. Microw. Theory Techn., vol. 68, no. 5, pp. 1717–1728, May 2020, doi: 10.1109/TMTT.2020.2979844.
[18] H. Lyu, Y. Cao, and K. Chen, “Linearity-enhanced quasi-balanced Doherty power amplifier with mismatch resilience through series/parallel reconfiguration for massive MIMO,” IEEE Trans. Microw. Theory Techn., vol. 69, no. 4, pp. 2319–2335, Apr. 2021, doi: 10.1109/TMTT.2021.3056488.
[19] H. Lyu and K. Chen, “Wideband quasi-balanced Doherty power amplifier with reciprocal main/auxiliary setting and mismatch-resilient parallel/series reconfiguration,” in Proc. IEEE MTT-S Int. Microw. Symp. (IMS), Atlanta, GA, USA, Jun. 2021, pp. 736–739, doi: 10.1109/IMS19712.2021.9575018.
Digital Object Identifier 10.1109/MMM.2022.3226549