Christian Carlowitz, Marco Dietz
©SHUTTERSTOCK.COM/ARTHEAD
Wireless communication faces ever-growing demand for higher data rates, which has driven the need for modem implementations that are capable of providing single-link data rates on the order of 100 Gb/s and beyond for extremely fast data transmission. In recent years, the 60-GHz band has been employed to significantly increase wireless local area network data rates in IEEE’s 802.11ad standard targeting multigigabit modems. Its extension 802.11ay was finalized in 2021, targeting data rates toward 100 Gb/s in the same bands by increasing spectral efficiency and combining up to four channels with more than 8-GHz bandwidth in total [1]. This approach has the advantage of existing unlicensed regulatory allocations. Nevertheless, options for higher bandwidth have increasingly been investigated, also driven by the publication of the IEEE 802.15.3d [2] physical layer standard for a frequency range between 252 and 325 GHz, which resides in an atmospheric window that enables reasonable long-range communication links on the order of a few kilometers. In this frequency range, a substantially higher bandwidth is achievable. Specific regulatory allocations are still missing; nevertheless, the conditions to use this frequency range have already been discussed and described during the 2019 World Radiocommunication Conference [3]. Although the first demonstrations of 100-Gb/s modems in this frequency range were at least partially based on photonic technologies [4], integrated front ends in different semiconductor technologies have been demonstrated [5] and are discussed in the present article in more detail together with the major remaining challenges for practical applications.
There are three fundamental approaches toward high data rates: increasing spectral efficiency (more bits per Hertz), using a larger bandwidth, and applying spatial diversity. In this article, we focus on single-link (single-input, single-output) 100-Gb/s techniques, while spatial diversity can be considered an additional option. We disregard multiple-input, multiple-output (MIMO) approaches with overall high throughput in a multiuser system or multipath environment. Nevertheless, polarization diversity is a similar approach that can be applied to combine two single links between two modems in a line-of-sight transmission that does not need to rely on multipath propagation or multiple user devices.
The current implementations for wireless local area networks or cellular mobile communication systems are based on very similar transceiver architectures (Figure 1). These implementations employ a zero-intermediate-frequency (IF) (also called “direct up- and downconversion”) homodyne front end, which up- and downconverts RF signals to and from the quadrature baseband with an RF local oscillator (LO) and quadrature mixers. The popularity of this approach is driven, for example, by its efficient usage of analog bandwidth, which also keeps the required analog-to-digital converter (ADC) and digital-to-analog converter (DAC) sampling rates low, the area- and power-efficient implementation in CMOS technologies, and high flexibility in terms of modulation schemes. In addition, baseband filters are easier to integrate in zero-IF architectures. To exploit as much channel capacity as possible, orthogonal frequency domain modulation (OFDM) is applied to adapt to nonidealities, such as channel fading.
FIGURE 1. Transceiver architectures can be mostly separated into three fundamental approaches for modulation and demodulation. (a) A homodyne transmitter (Tx) generates baseband in-phase and quadrature phase signals, with digital-to-analog converters (DACs) representing the real and imaginary components of the modulation vector, which are applied to the carrier by a quadrature mixer. This approach allows for direct amplitude and phase modulation. (b) A heterodyne Tx needs only a single baseband signal, which already contains a low-frequency carrier signal that is digitally generated before digital-to-analog conversion. This approach requires only a single input mixer but produces two sidebands next to the local oscillator (LO) frequency. One of these sidebands needs to be suppressed, for example, by a filter. (c) A polar Tx separates the modulation process into a consecutive phase and amplitude modulation. Many options exist for implementation, often employing digital or digital–analog hybrid circuits (the figure shows analog modulators), hence allowing for higher efficiency. The phase modulator, for example, can operate in or close to compression, and amplitude modulation often involves an amplifier modulation for more efficient amplification. In the receiver (Rx), similar approaches are employed for (a) and (b), while polar Rxs are uncommon. PA: power amplifier.
Scaling toward significantly higher data rates, however, introduces substantial challenges. In general, there are two options to increase the data rate: increasing the spectral efficiency or increasing the bandwidth. High spectral efficiency, that is, applying modulation schemes, such as 32 quadrature amplitude modulation (QAM) or higher, comes with the challenge of exponentially increasing the demand for high linearity and a high signal-to-noise ratio (SNR) with the number of bits accommodated in each transmitted symbol. Although high linearity can be achieved to some degree through circuit design and optimization, a high SNR requires either higher transmit power or sacrificing range coverage. As already discussed in [5], it is worth considering whether high spectral efficiency in a bandwidth-limited operation mode can be an effective approach. In early beyond 10-Gb/s publications, low-spectral-efficiency schemes were investigated for the 200- to 300-GHz frequency range [6]. In addition, according to Shannon’s theorem, channel capacity increases linearly with bandwidth compared with an only logarithmic increase with the SNR. Thus, achieving a faster communication link through boosting the number of bits per bandwidth comes at a very high cost. Because the output power is technology limited, range coverage severely drops with high-order modulations, but they may be attractive in the case of mobile transceivers in close vicinity to the base station. Consequently, most implementations consider 16 QAM or less when targeting longer transmission distances. Using amplitude modulation only would simplify hardware considerably because no coherent demodulation is needed, so LO generation and phase noise performance are less critical. Nevertheless, most studies consider at least quadrature phase shift keying (QPSK) because it does not reduce the power level budget. The distance of the constellation points in the in-phase and quadrature phase (I/Q) plane is better than with amplitude shift keying (ASK) or on–off keying with same maximum transmit power while doubling throughput, if we consider additive white noise as the major error source.
Given that a coherent transmission principle is set, there are different approaches for implementation beyond the homodyne receiver (Rx). Although heterodyne concepts using an IF require a large analog bandwidth, these concepts could be attractive because no quadrature mixer is required, which needs higher LO power and a high-bandwidth quadrature generation network. This network often also requires I/Q correction (e.g., frequency-dependent phase adjustment), especially for broadband applications. The heterodyne bandwidth requirement can be reduced by using a very high relative bandwidth with a low-frequency IF; that is, the IF frequency is only slightly above half of the used channel bandwidth. Consequently, ADCs and DACs need a little bit more than twice the bandwidth and sampling rate compared with the two homodyne baseband converters. However, doubling the bandwidth and sampling rate may lead to substantially higher power consumption and could be challenging to implement in CMOS technologies.
Single-carrier high-bandwidth transmission requires a flat frequency response and a linear phase for intersymbol interference-free detection. Although equalization applied as a postcorrection operation enables removing such interference, it requires a significant amount of digital signal processing with high-power dissipation and reduces the available SNR for demodulation. Thus, multiband homodyne and heterodyne transceivers are alternatives that split the bandwidth into subchannels with lower bandwidths and individual modems for transmission. Coherence between the carriers is not necessarily required like with OFDM techniques, but noncoherent channels come with a loss of bandwidth because of the interchannel spacing requirements for bandpass filtering.
There are several general semiconductor technologies commercially available for actual RF integrated systems. Because of advances in the field of CMOS technologies, the field of possible semiconductor technologies for integrated D-band and terahertz (THz) systems has expanded in recent years [7]. For wireless transceivers of 100 Gb/s and beyond, the previously mentioned frequency ranges are preferred because of their natural high absolute bandwidth, which can be achieved with a moderate relative bandwidth. This relaxes the design of integrated components. However, at these high frequencies, key parameters, such as output power, noise, gain, linearity, and power consumption, become worse compared with components realized at lower frequencies. To overcome the decreasing performance parameters, improved circuits architectures can be used. A very important factor to the performance parameters concerns innovative semiconductor technologies. The semiconductor technology itself has a very strong influence on the performance of circuits at these frequencies. Example characteristics are the well-known ${f}_{T}$ and ${f}_{\max}$. In this article, the focus is on two popular silicon (Si) technologies and two widely used III-V technologies. For the Si representatives, we briefly summarize the fully depleted Si-on-insulator (FDSOI) CMOS and silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) in Bipolar CMOS (BiCMOS) technologies. FDSOI CMOS is one of the CMOS family representatives, while the well-known bulk CMOS technology is omitted, although it is also used for realizing high-data-rate front ends. Later on in this section, III-V technologies are briefly discussed.
Compared with its SiGe HBT counterpart, the FDSOI MOSFET is, in general, a lateral device, which means that the charge carrier flow is in the lateral direction. This physical difference provides an additional noise contribution. Of course, the overall noise performance of a transistor is generally determined by many other parameters, such as the gate length for CMOS transistors or the base width for bipolar transistors, respectively. Compared to other semiconductor technologies, CMOS has lower intrinsic gain. These two disadvantages can be compensated by multistage architectures in amplifiers. Modern FDSOI CMOS technology offers a high ${f}_{T}$ and ${f}_{\max}$, which makes this kind of CMOS technology suitable for RF components and systems in millimeter-wave (mm-wave) and sub-THz ranges. An example here is the 22FDX technology of Global Foundaries, which offers ${f}_{T} = {347}{\text{ GHz}}$ and ${f}_{\max} = {371}{\text{ GHz}}$ N-type field-effect transistor (FET) devices and ${f}_{T} = {275}{\text{ GHz}}$ and ${f}_{\max} = {299}{\text{ GHz}}$ P-type FET devices. [8] This technology exhibits also two thick upper metal layers. These layers are well suited for passive RF components and allow, at the same time, high currents in the milliampere range. The biggest advantage of the FDSOI technology compared to the other technologies mentioned is the very high integration density. In terms of 100 Gb/s and beyond, FDSOI CMOS allows very compact systems, which bring a multichannel front end and powerful baseband circuity on the same chip together [8], [9].
Modern HBT technologies, as described in [10], from the Leibniz Institute for High Performance Microelectronics (IHP), offers SiGe transistors with ${f}_{T}$ and ${f}_{\max}$ up to 505 and 720 GHz, respectively, which is the actual world record. The SiGe technology proposed in [10] offers transistors with a collector–emitter breakthrough voltage ${(}{BV}_{\text{CEO}}{)}$ of 1.6 V, which is usual for HBT transistors with such an ${f}_{T}$ and ${f}_{\max}$ of several hundred gigahertz. Compared with current FDSOI-based CMOS technologies, this is a much higher value. Furthermore, compared with standard CMOS technologies, SiGe-based technologies offer mostly two thick upper layers in the back end of the line, which allows good performance for inductive devices, such as inductors and transformers [11], [12], [13]. In modern FDSOI CMOS technologies, this drawback is eliminated by adding thick top metal layers, as previously described.
The history of metamorphic high-electron mobility transistors (mHEMT) dates back to 1980. In that year, Fujitsu, in Japan, fabricated the first mHEMT transistor. [14] Today, the mHEMT technology is often used for high-performance applications that appear as the first Rx or transmitter (Tx) stage. Examples can be found in [6], [15], and [16]. Compared to SiGe-based HBT transistors or FDSOI CMOS transistors, in mm-wave and sub-THz designs with a state-of-the-art mHEMT technology, a lower noise figure and higher output power, respectively, can be reached. In terms of communication systems, this enables a comparatively higher operating range for a minimum required bit error rate. In satellite communication systems, mobile backhauling, wireless personal networks, and some other applications, compact and high-performance RF Txs and Rxs now become possible. A disadvantage of some available mHEMT processes is the comparably low number of metal layers [17], [18]. This avoids complex multichannel front ends with complex control circuits. However, in modern beam steering MIMO front ends, this can be a limitation. According to [17], the long-term operation range for bias voltages in mHEMT devices is between 1 and 1.5 V, which was originally described in [18]. This leads to a lower output power level compared with their indium phosphide (InP)-based HBT counterparts for a single transistor stage.
InP is used for both HBT transistors and HEMT transistors. In 2015, the first reasonable amplification at 1 THz for an InP HEMT process was shown [19]. The InP transistors of this process exhibit an ${f}_{T}$ of 610 GHz and ${f}_{\max}$ of 1.5 THz. According to [19], an on-state burnout voltage ${(}{BV}_{\text{onstate}}{)}$ of 2.2 V and an off-state burnout voltage ${(}{BV}_{\text{offstate}}{)}$ of 3 V make an operation range up to ${V}_{\text{ds}}$ of 1.5 V possible. A drawback is the relatively low number of metal layers. InP-based HBT transistors usually exhibit bias voltages of 1.8 to 2.2 V [17], which enables high-power devices as well as the InP HEMT transistors. As an example, Teledyne Scientific’s 130-nm InP HBT integrated circuit (IC) technology offers a ${BV}_{\text{CEO}}$ of 3.5 V [20], which is much higher compared with the aforementioned FDSOI CMOS and SiGe HBT technologies. With an ${f}_{T}$ of 250 GHz and ${f}_{\max}$ of 1.15 THz, the InP HBT transistors are well adapted for THz applications, like the InP HEMT technology as well.
The main question before starting product development is the choice of the semiconductor technology. On the one hand, there are semiconductor technologies out of the III-V family that offer better performance in terms of intrinsic gain, noise behavior, and achievable output power for applications in the mm-wave and THz-ranges. However, complex front ends are more difficult to realize than in their Si counterparts. This may also come with higher production cost and availability depending on production volume. On the other hand, Si-based technologies, such as SiGe HBT and FDSOI CMOS, overcome these challenges, with good RF performance. These technologies are optimized for complex front ends, and in the case of FDSOI CMOS and BiCMOS, the baseband circuitry can be directly integrated on chip. Due to new packaging technologies [21], different chip dies can be integrated into a common package, which allows cointegration of III-V-based building blocks, such as power amplifiers (PAs), low-noise amplifiers (LNAs), and Si-based front and back ends. The choice of the semiconductor technology depends strongly on the application [7].
In the following, we discuss several implementations that have been demonstrated at, or are approaching, data rates of 100 Gb/s. They are sorted by technology and frequency range.
Research targeting 100 Gb/s is not limited to the THz frequency range, that is, frequencies well above 100 GHz. The IEEE 802.11ay standard [22], which was finally approved in 2021, defines a physical layer for frequencies above 45 GHz, with a bandwidth ranging from 2.16 to 8.64 GHz, increasing the achievable throughput over the previous IEEE 802.11ad standard. The primary frequency range being targeted is 57 to 71 GHz, which is allocated for unlicensed use. A theoretical data rate of 42.24 Gb/s can be achieved using 64 QAM (6 b/symbol) in the widest bands. For dual polarization, this could be doubled. Further throughput enhancements are possible through multiple MIMO streams. Even though the standard does not specify single links with 100 Gb/s or more, it is considered to be a “100 Gb/s Wi-Fi” standard [1]. In the following, we go over the current implementations that achieve the highest data rates demonstrated so far [23], [24], [25]. These are based on CMOS technologies and use different approaches to achieve high data rates as well as high energy efficiency per transmitted bit.
In [23], a 65-nm CMOS transceiver has been shown to transmit 50.1 Gb/s (single stream, single polarization) over a 3-cm air gap, with 14-dBi antennas, 7.3-dBm transmit power, and an energy efficiency of 3.4 pJ/b for the Tx and 2.8 pJ/b for the Rx (see Figure 2). A Tx-to-Rx error vector magnitude (EVM) of −23.3 dB was achieved. It employs a homodyne (direct conversion) architecture with an external 8.35-Gbaud 64-QAM baseband and chip-integrated LNA, PA, and up/downconversion, including LO generation. A quadrature injection-locked oscillator (Q-ILO) has been implemented to generate 90° phase-shifted LO signals for the I/Q mixers. The IC includes a phase-locked loop that locks the divide-by-three Q-ILO signal to a 36-MHz external reference. Like in all homodyne architectures, I/Q imbalance is a concern, especially when targeting 64 QAM or even 128 QAM, requiring more than 50 dBc of detection sensitivity. Because high bandwidth and a high-resolution amplitude detector would be needed at the Tx output for I/Q imbalance analysis over the whole IF bandwidth, a quadrature IF downconversion block is implemented to reduce the bandwidth requirements, thus enabling two efficient 10-b 10-MS/s successive approximation ADCs for Tx characterization.
Figure 2. A 50.1-Gb/s 60-GHz CMOS transceiver (Tokyo Institute of Technology) [23]. (a) Transmitter and receiver block diagrams. (b) IC micrograph (left) and measured I/Q-constellation diagram (right). PLL: phase-locked loop; Q-ILO: quadrature injection-locked oscillator; VGA: variable gain amplifier; BB: baseband.
In [25] and [24], Tx and Rx 28-nm CMOS front ends are demonstrated that implement dual-polarization transmission with 42 Gb/s and a 2 × 2 beamforming Rx array with 64 Gb/s to/from a test Rx/Tx built from laboratory equipment (see Figures 3 and 4). Both ICs employ a homodyne architecture, but the Tx features a digital-enabled polar modulator similar to an RF DAC, whereas the Rx is based on a quadrature downconverter. Although the Tx approach limits the system to direct carrier modulation—whereas a quadrature system can support OFDM—polar Txs are well known to achieve better power efficiency. By employing a digital approach toward modulation, a significant amount of power can also be saved by avoiding high-resolution data converters, which are typically not part of most front-end demonstrations but are required for operation and will significantly increase the total power dissipation in most concepts. The Tx is based on a digital driver concept, which includes an interpolating finite-impulse response filter and configurable edge rate driver for each modulator bit. These circuits allow for very efficient spectral shaping to meet the standard’s spectral mask. Phase modulation is based on a phase-only quadrature modulator based on two 5-b ASK modulators. Amplitude modulation is achieved through a digital PA, which combines the output signals of five amplifier cells with a 5-b ASK input. In terms of the output power, a peak of 11.5 dBm is reached, with a 6-dBm average, at 42.2 Gb/s, with 64 QAM and 3.52 Gbaud each on horizontal and vertical polarization. The spectral efficiency is 4.3 pJ/b for the Tx, excluding LO generation, which requires an external 2/3 frequency input (38–48 GHz), while frequency division (factor 2) and multiplication (factor 3) as well as I/Q generation are performed on chip. The divide-by-two circuit probably serves as an ultrabroadband flip-flop-based quadrature generation block. A tripler allows for upconversion while retaining a 90° phase shift.
Figure 3. A 42-Gb/s Tx dual-polarization 60-GHz CMOS transceiver (Intel) [25]. (a) Transmitter block diagram. (b) Chip micrograph (left), measured transmitter I/Q constellation diagrams for horizontal (center) and vertical polarization (right). CLK: clock; SRAM: static random-access memory; FIR: finite-impulse response; PM: phase modulation; AM: amplitude modulation; DPA: digitally switched power amplifier.
Figure 4. A 64-Gb/s Rx dual-polarization 60-GHz CMOS transceiver (Intel) [24]. (a) Receiver baseband I/Q constellation diagram for (left) vertical polarization; chip micrograph (right). (b) Receiver baseband I/Q constellation diagram for horizontal polarization.
The Rx uses a classic homodyne downconversion with a double-balanced I/Q mixer and a similar 2/3 LO input and I/Q generation chain like in the Tx. A special Rx feature is the two-by-two beamforming array, which targets spatial interference mitigation. Each of the four inputs comes with a single-stage LNA (19-dB voltage gain), active phase shifters for avoiding noise figure degradation, and a lumped RF combiner. A total data rate of 64 Gb/s is achieved in dual-polarization MIMO, with 16 QAM (8 Gsym/s × 4 b/pol × 2 pols) and –19.2-dB EVM. The energy efficiency of the Rx is 1.4 pJ/b, which can be considered an outstanding value.
Different approaches with higher carrier frequencies than 71 GHz have been demonstrated with the goal of exploiting the area- and power-efficient implementation opportunities offered by CMOS.
In [26], a 65-nm CMOS transceiver with heterodyne architecture is presented, which achieves 120 Gb/s by utilizing two bands at 70 and 105 GHz, with 15 Gbaud and 16 QAM (60 Gb/s each), which are power combined before power amplification (see Figure 5). The LO signals for both bands operate from a 35-GHz external source, which is doubled in frequency for the low band and tripled for the high band and, in both cases, amplified in two stages. Two double-balanced mixers upconvert the baseband signals for both bands, which are centered around an IF of 8.75 GHz, with a 17-GHz analog bandwidth. For the low band, the upper sideband is used, and for the high band, the lower sideband is used. In this way, the image frequencies are outside the frequency ranges used for transmission. The Rx path uses the same principle. Before power combining in the Tx and after power splitting in the Rx, RF buffer amplifiers are implemented, which offer a band-matched transfer function; they are optimized for in-band signal amplification and out-band suppression of unwanted sidebands at the same time. In case of the Rx, all adjacent bands are suppressed. For the Tx, image suppression is the focus. The cross talk between both bands is low, with 0.9-dB EVM degradation. A six-stage PA delivers −1.9-dBm output power, and a five-stage LNA improves the Rx noise figure. The total power consumption for the Tx is 120 mW and 160 mW for the Rx. Thus, the energy efficiency is 1 and 1.3 pJ/b, respectively. Transmission is demonstrated over a 20-cm air gap, using two 23-dBi horn antennas connected to the IC via a waveguide transition (10-dB module loss) and an EVM of 16.9 dB.
FIGURE 5. A dual-carrier 70/105-GHz 120-Gb/s CMOS transceiver (Tokyo Institute of Technology and Fujitsu) [26]. (a) Transmitter (left) and receiver (right) block diagram, receiver baseband I/Q constellation diagram (center). (b) Chip micrograph. HB: high band; LB: low band; SPI: Serial Peripheral Interface.
In [27] and [28], a 40-nm CMOS transceiver is demonstrated that can generate and receive signals at 265 GHz, with 16 QAM and 20 Gbaud (80 Gb/s). Because frequencies around 300 GHz are at or beyond the maximum frequency of the underlying process, passive frequency multiplication is required for upconversion. A mixer-first approach is required for downconversion. The Tx employs a zero-IF homodyne quadrature mixer stage with an intermediate LO frequency of 132 GHz. Further upconversion is performed with a square mixer, which creates intermodulation products from the IF and the 132-GHz LO leaking through the quadrature mixer (approximately −10 dBm, according to simulations), which is implemented by applying a dc voltage to the I/Q inputs. Because a square mixer does not generate only the desired intermodulation product between the LO and IF but also the doubled LO frequency and the doubled modulated IF signal, a second Tx path is added, with inverted I and Q signals. When both Tx paths are combined in a rat race hybrid, the difference output shows only the desired intermodulation product. This happens because the squared LO and IF signals from the unshifted and 180°-shifted transmit paths have the same sign, while the intermodulation products have differing signs. To improve the output power, a double-rat-race hybrid is used, which accepts additional 0 and 180° inputs that are power combined at the output. Additional amplifier and square mixer paths supplied from the quadrature mixer outputs deliver additional signal power. The hybrid’s sum output contains the doubled LO and IF signals. If no modulation is applied to the Tx mixer inputs, this port provides the LO for the Rx mixer (see Figure 6). The Rx front end is a straightforward mixer-first homodyne quadrature downconverter with baseband amplifiers. The setup draws 1.79 W, resulting in an energy efficiency of 22.4 pJ/W while transmitting over a 3-cm air gap. It is limited by the Rx performance as well as by insertion losses from waveguide connections between chip and antenna.
Figure 6. A 300-GHz 80-Gb/s Tx/Rx and 105-Gb/s Tx frequency-doubling CMOS transceiver (Hiroshima University) [27], [28]. (a) Transmitter (left), receiver (right), and local oscillator generation network (bottom) block diagrams. (b) Chip micrograph (left), measured receiver baseband I/Q constellation diagram (right, top), and received spectrum (right, bottom; x-axis: frequency in GHz, y axis: relative power in dB). SDBQM: semidoubly balanced quadrature mixer; RMS: root mean square.
In [29], a similar 40-nm CMOS Tx is demonstrated, which achieves 105 Gb/s, with 32 QAM modulation. Instead of quadrature modulators, an IF mixer around 10 GHz with a lower sideband rejection filter (quasi-single-sideband mixer) simplifies the upconversion. With an LO input around 48 GHz and a tripler, a carrier frequency around 150 GHz is achieved. A rat race balun is used instead of a hybrid. Additionally, the number of square mixer channels is doubled using two-way power splitter and combiner networks. The circuit delivers −5.5-dBm output power at 300 GHz while consuming 1.4 W, which results in energy efficiency of around 13 pJ/W (Tx only).
In [30], classic homodyne 240-GHz Txs and Rxs in 130-nm SiGe BiCMOS are presented, which use fundamental I/Q mixers for up/downconversion, with an LO input at 30 GHz, which is multiplied by a factor of eight in total (see Figure 7). A transmit power of 12 dBm is generated using a three-stage predriver followed by a four-way PA with a total 3-dB bandwidth of 55 GHz. The Rx features a three-stage LNA followed by quadrature downconversion with the same LO network as in the Tx. A total Rx gain between 16 and 41 dB is achieved, and tunability is provided by a baseband variable gain amplifier. Both ICs exhibit integrated dipole on-chip antennas with a printed circuit board (PCB)-based backplane and 4 × 4-cm dielectric lenses, delivering a total antenna gain of 21 dBi. A data rate of 100 Gb/s is reached over a 0.8-m link with 25 Gs/s, 16 QAM, and an EVM of 18.6%. The Tx and Rx circuits consume 0.85 and 1.24 W power, respectively, thus achieving a total link efficiency of 21 pJ/b.
Figure 7. A 100-Gb/s 240-GHz SiGe transceiver (IHP) [30]. LBE: localized backside etching; TIA: transimpedance amplifier.
A 230-GHz transceiver implemented in 130-nm SiGe is demonstrated in [31] and is based on a classic homodyne architecture (Figure 8). It is relatively similar compared with the IHP chipset [30] discussed in the preceding paragraph, but differs especially in LO multiplication factors, PA stages, and the Rx mixer configuration. The LO input allows for a lower-frequency input (13.75 to 16 GHz), which is achieved through a higher multiplication factor of 16 and implemented using four cascaded Gilbert cell doublers. The PA consists of four stages but does not have an n-way front end, which results in a lower output power of 5 dBm. The Rx [32] uses a mixer-first instead of an amplifier-first approach for improved sideband symmetry, at the expense of the conversion gain and noise figure. A similar earlier amplifier-first version [33] provides only slightly better noise, at 11 dB instead of 14 dB. During transmission over a 1-m air gap, 100 Gb/s is achieved (17% EVM), with 25 Gbaud and 16 QAM with 25–27-dBi antennas based on a combination of on-chip patches radiating through the chip substrate and a 9-mm Si lens. Power consumption is 0.96 W for the Tx and 0.45 W for the Rx, leading to a total efficiency of 14 pJ/b. The majority of the power consumption is drawn by the LO generation circuitry, with 860 mW in total.
Figure 8. A 100-Gb/s 230-GHz SiGe transceiver (University of Wuppertal) [31]. (a) Transmitter and receiver block diagram. (b) Module assembly photo (left) and receiver baseband I/Q constellation.
Higher-order modulation (32 QAM) is shown in [34] with an amplifier-first Rx but lower data rates (90 Gb/s, 15% EVM). In [35], lower-order modulation (QPSK) is investigated in conjunction with a dual-polarization Tx and Rx, which relaxes the baseband requirements for the DAC and ADC because only binary signals are required for the I/Q phase channels. Antennas with circular polarization (left hand and right hand) enable alignment-insensitive transmission, thus avoiding analog or digital postprocessing circuits for depolarization. With a similar front-end approach compared with [31], an aggregate data rate of 110 Gb/s (2 × 27.5 Gbaud) is achieved at 230 GHz with 31.9% EVM over a distance of 1 m. The worst-case isolation between the two transmission path polarizations is 18 dB, which includes both antenna and front-end nonideal isolation. In terms of power consumption, the circuits draw 2.85 W, which results in 25.9 pJ/b compared with 0.95 W and 14 pJ/b in the single-channel version from [31].
In [36], a similar dual-polarization chipset is discussed to identify the limitations in scaling toward a higher bandwidth and data rate. One major aspect is the asymmetry between the lower and upper sideband of the I/Q transceiver when occupying a very large bandwidth that occurs because of increasing losses when approaching the transition frequency. Further error sources include broadband phase noise, harmonic spurs from the LO multipliers, baseband port isolation, and quadrature errors. Some of these aspects are discussed in more detail in the “Discussion and Challenges” section.
In [37], homodyne Tx and Rx mHEMT indium gallium arsenide (InGaAs) monolithic microwave ICs are demonstrated in a 40-m wireless link at 240 GHz, with 96 Gb/s and 8-PSK modulation with an EVM of 21.6%. The chipset (see Figure 9), which is discussed in more detail in [38], with its waveguide module packaging in [39], is based on a 35-nm gate length technology for the Rx and 50 nm for the Tx to better optimize for lower noise and a higher output power, respectively. Both circuits share an LNA and quadrature mixer design. The mixer operates as a subharmonic mixer with an LO input at 120 GHz. It is based on a resistive transistor mixer with a balanced configuration for better LO-to-RF isolation. A Lange coupler at the RF port performs quadrature generation and combination. For low-noise amplification, a four-stage cascode amplifier design delivers 20-dB gain and a noise figure of 4.8 dB in the Rx. The Tx employs only three stages, with up to 1-dBm output power and −3.6 dBm for the packaged module. Its output power is technologically limited, already showing compression, which limits the modulation format to n-PSK. Nevertheless, a high-IF frequency range from 0 to 40 GHz and RF bandwidth from 220 to 260 GHz enable a very high symbol rate of 32 Gbaud, thus almost reaching 100 Gb/s.
Figure 9. The 96-Gb/s 240-GHz and 64-Gb/s 300-GHz InGaAs transceivers (University of Stuttgart and Fraunhofer Institute for Applied Solid State Physics) [37], [38]. (a) Transmitter chip micrograph (left), transmitter I/Q constellation diagram (right). (b) Transmitter and receiver block diagrams. MMIC: millimeter-wave monolithic integrated circuit.
In [16], a 300-GHz chipset using a similar approach is introduced, which additionally integrates an LO tripler for driving the single-balanced resistive FET quadrature mixer and a 3.6-dBm-output PA with a two-way stage at the Tx output. Its mixer also targets a dual-channel superheterodyne operation based on extending the frequency range of lower-frequency wideband transceiver chipsets. Thus, the I and Q channels can also be used to simultaneously upconvert two channels of existing modems in the 70-GHz frequency region, which is discussed in [40]. Different modulations have been tested, for example, 64-Gbit/s QPSK, 60-Gbit/s 16 QAM, 12-Gb/s 64 QAM, or 2 × 8-Gb/s 32 QAM in dual-channel configuration. The chipset has also been analyzed in terms of modulation and baud rate considerations in [41], where compression and phase noise are identified as major error sources for PSK and, especially, QAM modulation formats. 8-asymmetric PSK (APSK), which resembles a QPSK constellation diagram with an additional smaller-amplitude and 45°-rotated QPSK in its center, is evaluated. It shows better resistance toward phase noise and compression, which strongly affect outer constellation points in 16 QAM and higher.
In [42], higher-order modulations are investigated by targeting 802.15.3d channels, using the superheterodyne approach with different configurations. The highest data rates are shown with a 79.1-GHz IF and 32 QAM (8.64-GHz bandwidth, 32 Gb/s), which is considered limited mainly by the measurement equipment’s frequency coverage, and the linearity is sufficient for 256 QAM with lower bandwidth (1.35 GHz, 1 Gbaud, and 8 Gb/s).
In [43], a 300-GHz heterodyne Tx and Rx in 80-nm InP HEMT technology (300/700-GHz f T/f max) is demonstrated; it achieves 120 Gb/s with 16-QAM modulation over a link distance of almost 10 m (Figure 10). Although it differs from the other transceivers presented so far in the sense that it is not a fully integrated chipset but an assembly of waveguide-packaged components, it needs to be considered here because of its high performance and same technology implementation of most components. For packaging, waveguide modules with ridge coupler-based transitions and less than 1 dB of insertion loss are employed. The only non-IC-based module is a high-pass filter for lower sideband rejection in the Tx.
Figure 10. A 300-GHz 120-Gb/s InP transceiver (NTT and Tokyo Institute of Technology) [43]. (a) Transmitter and receiver block diagrams. (b) Power amplifier chip micrograph (left), mixer chip micrograph (center), and received baseband I/Q constellation diagram (right).
Because the circuits operate at the transit frequency of the InP process, amplification is a crucial part of the system. The main component is a two-stage eight-way power combined network, where each amplifier stage consists of a six-stage amplifier cell. A low-impedance interstage matching technique reduces matching losses, which helps in enabling a high gain and output power. A 6.8-dBm 1-dB compression point and a 12-dBm saturation power level are achieved between 278 and 302 GHz, with 21-dB maximum gain and a very flat frequency response. For LO amplification, two cascaded PAs are employed, and an additional single one is used as the RF PA. The same circuit also serves as an LNA with a noise figure of around 15 dB at 300 GHz. Frequency multipliers for LO generation are externally provided by laboratory equipment with an output frequency of 270 GHz. A mixer IF of 20 GHz guarantees sufficient 3-dB bandwidth for the 32-GHz transmission channel. At 30 Gbaud with 16 QAM, 120 Gb/s are demonstrated, and 1.5-dBm single-PA transmit power can be achieved. A dual-PA configuration allows for 6-dBm transmit power but has lower bandwidth, which limits the data rate to 100 Gb/s. Power consumption is 4.5 W for both the Tx and Rx, leading to an energy efficiency of 75 pJ/b.
The first demonstration of 100-Gb/s wireless transmission was based on photonic technology [4], though a fully integrated front end has not yet been implemented so far; thus, we do not discuss these approaches in detail. Nevertheless, the highest demonstrated data rates so far—well beyond 100 Gb/s—use optical technologies, especially for signal generation at THz frequencies, using unitraveling carrier (UTC) photodiodes. Typically, an optical quadrature modulator is used to generate the desired communication signal on an optical carrier, which is then combined with a continuous wave optical reference signal that is offset by the desired THz carrier frequency. The THz output signal is radiated from a UTC photodiode, operating as a mixer for the two optical carriers through a horn antenna. Reception and downconversion are typically performed using electronic approaches, which is similar to what has been shown in the preceding and is often based on waveguide-packaged components with passive zero-IF or IF downconversion. Photonic components have the advantage that a modulation bandwidth of even 100 GHz and beyond still constitutes a narrowband signal at typical near-infrared optical frequencies of around 193 THz (1,550 nm), which are employed in telecom equipment and thus are widely available. Reference [44] provides an overview of THz photonics for communication. Current implementations include, for example, a 400-GHz 106-Gb/s (16-QAM) link in [45], which is similar to what is found in [46] and [47]; [48] demonstrates 300 Gb/s with six 12-Gbaud 16-QAM channels between 300 and 500 GHz.
Although the current wireless links have already demonstrated mostly complete integrated front ends, there are still implementation aspects that remain challenging and require further research and development. They can mostly be boiled down to power dissipation, efficiency, packaging, spurious signals, phase noise, and application scenarios. Some of these aspects have already been discussed recently, for example, in [49] from a beyond 5G/6G perspective and in [5] from a THz communications perspective.
With higher frequencies, the geometrical path loss notably increases when the antenna gain remains unchanged. The maximum feasible antenna gain is typically dominated by the application; that is, a mobile application requiring high spatial coverage needs larger radiation angles and smaller antennas, which are also shape optimized and eventually combined into phased arrays, whereas stationary point-to-point wireless links may use large horn antennas, dielectric lenses, or dish antennas. Therefore, transmit power can be considered a critical parameter, especially when moving toward THz frequencies. The implementations discussed in the preceding provide an output power of around only 1 mW or less, with moderate power consumption, while the lower-frequency systems in CMOS technology deliver around 10 mW or more. The output power is both limited by technology (maximum voltage and losses) and by the allowable thermal dissipation. All implementations extensively use multistage amplifiers to achieve sufficient gain for LNAs, PAs and LO multipliers, and mixer driver amplifiers. Thus, power dissipation is dominated by the amplifier chains. A higher output power beyond single-stage technology limits can be achieved only through n-way passive power combiner networks driven by multiple amplifier chains, at the expense of also multiplying power dissipation. Consequently, lower-frequency implementations have a significant advantage in many ways: lower geometric path loss for a certain antenna gain; higher output power and, thus, range coverage; and lower power dissipation thanks to more efficient and higher-gain amplifiers. Thus, high available bandwidth from moving toward higher-frequency bands still comes at a relatively high cost. In addition, the corresponding frequency bands are not yet allocated, and communication standards still need to be completed.
All THz-based approaches operating between 200 and 300 GHz make intensive use of frequency multipliers for LO generation and also some lower-frequency implementations. Fundamental oscillators become increasingly difficult to implement at high frequencies, especially because the transit frequency is approached in many semiconductor technologies. Given that phase noise is a critical performance figure (see the following) [50], low-noise sources are required, which are easier to implement at lower frequencies. Although additional noise power density is added through frequency multiplication beyond the theoretical noise increment of the squared multiplication factor, the benefits often outweigh the downsides in terms of the overall noise performance. However, spectral purity remains an issue because undesired harmonics are generated in the multiplication process that are often hard to suppress completely. When using high multiplication factors, harmonics and their intermodulation product may fall into the frequency range used for transmission [31], thus limiting the effectively usable bandwidth. Similar effects may also occur through limited isolation between the high-power-level LO frequency input and baseband ports [31].
Even with very high bandwidth at THz frequencies, coherent transceivers and modulation schemes are required for sufficient spectral efficiency to support data rates of 100 Gb/s. QPSK, and often also 16 QAM, are considered for transmission. Thus, a coherent and sufficiently stable frequency reference is required as an LO for the Tx and Rx. In the demonstration experiments discussed in the preceding, some authors have used a synchronized LO; that is, a common LO is distributed to both the Tx and Rx, using a power splitter. This approach facilitates accurate front-end characterization, but for practical applications, individual LO sources need to be integrated in the same or a separate nearby-positioned chipset. So far, all THz experiments mentioned are based on high-quality laboratory-grade signal generators as the LO source. Thus, LO noise will be a challenge when moving forward. In [31], the authors already show a significant contribution to random phase errors. High spectral efficiency strongly suffers from wideband white noise in the LO signal, which has been analyzed in [51]. Although white noise at high frequency offsets in the LO signal can be considered additive, it becomes a multiplicative noise contribution after modulation with the baseband symbols. Thus, outer constellation points in the I/Q plane are increasingly affected by both phase and amplitude noise, especially for QAM modulation (see Figure 11). Frequency multipliers also contribute to increased noise amplitude, at least in terms of phase noise, because the phase is multiplied with the conversion factor, and thus, the noise power increases with the squared factor. Therefore, [41] considers 8-APSK with larger constellation point distances but a still roughly equidistant distribution. As a possible solution, [51] proposes a narrowband LO bandpass filter after frequency multiplication, which is, however, challenging for chip integration at THz frequencies without significant area consumption and insertion loss.
Figure 11. The impact of different noise sources on the constellation diagram: 64-QAM modulation with (a) additive white noise, (b) phase noise, and (c) multiplicative white noise.
The wideband white noise contribution to phase noise also increases linearly with modulation bandwidth, so the combination of a high carrier frequency and high bandwidth poses a significant challenge. In this regard, [31] reports that even with a high-quality laboratory signal generator (PSG E8257D) and a factor-16 multiplier, the phase error magnitude contribution already accumulates 4°, which limits higher-modulation schemes, even at short distances where a sufficient power level budget would be available. In [50], wideband phase noise is also acknowledged as the major error source above 240 GHz, while near-carrier phase noise is considered negligible. As a possible solution, multicarrier transmission is proposed to enable higher spectral efficiency without degradation from phase noise.
A popular use case for 100-Gb/s communication systems is downloading a large amount of data, for example, video files, from a data terminal (kiosk) to a mobile device in an extremely short time (quasi-instant) over a short distance of 1 m or less. The scenario has been discussed and demonstrated, for example, in [5] and [52]. It is most challenging in terms of small-size integration, packaging, and power dissipation. Even in short-distance scenarios, a high antenna gain is needed for at least one side of the wireless link, typically the kiosk terminal (e.g., 15 dBi for the mobile device and 30 dBi for the terminal in [52], with 20-Gb/s ASK). As a result, alignment is a practical challenge. A beam steering technique is required for automatic alignment. Possible applications, apart from active phase shifter arrays, include microelectromechanical system-based beam steering, liquid crystal-based phase shifter arrays, or tunable metasurfaces [53].
Other scenarios consider long-distance transmission, which has already been demonstrated, for example, in [54], with 300-GHz transmission over 500 m with 16 QAM and 96 Gb/s (76-Gb/s netto). For these distances, an even much higher antenna gain is required, which, in this demonstration, is provided by two parabolic dish antennas with 55-dBi gain each. These antennas require very precise alignment, but the transmission channel is stable once successfully aligned. Atmospheric attenuation varied between 2 and 3 dB when environmental conditions changed between clear weather and light rain during a 10-h test operation. The requirements for the front ends can be considered relaxed in this case compared with mobile communication because at least the system size, packaging, and power dissipation are less critical in a stationary wireless link.
Many of the discussed implementations also calculate the power efficiency of the front end in terms of picojoules per transmitted and received bit. Although this information provides a rough indicator for how power efficiently the front end operates, it does not allow for an accurate comparison because the completeness of the implemented circuits varies, and many of the components for a full modem are missing for practical applications. Most notably, an LO source, data converters, and digital baseband processing are required. The efficiency of these components depends on their architecture and the requirements of the transceiver concept (e.g., analog bandwidth and dynamic range for ADCs and DACs). Baseband processing is, for example, discussed for a wireless link in [55], including channel equalization, I/Q imbalance correction, carrier frequency synchronization/estimation, and error correction algorithms. At high data rates, this digitally performed processing consumes a substantial amount of power, so it is worth considering whether some of these tasks can be omitted, for example, in favor of allowing a high bit error rate, which is reduced by relatively power-efficient error correction processors [56]. Equalization may be omitted if the front end has a linear phase and flat frequency response. If a maximum allowable total power dissipation of 1 W for a mobile 100-Gb/s modem is assumed as a reasonable expectation, the required energy efficiency would be 10 pJ/b. This value can be approached only by the most efficient CMOS implementations at 60 GHz but only for the front end itself without data converters and baseband. Therefore, substantial optimizations are still required for the mobile application scenario.
When moving toward practical applications of 100-Gb/s transceivers, they need to be integrated into communication modules, systems, and, possibly, mobile devices. Although current mobile communication and Wi-Fi modems rely on classic IC packaging with ball grid arrays soldered on PCBs with onboard or connectorized case antennas, high-mm-wave frequencies require other approaches because of the high substrate and transition losses. The discussed 200–300-GHz circuits radiate from the chip surface [30] or through the chip backside into a lens [31] or couple to a waveguide [39]. Because dc and baseband signals are also required, wire-bonded PCBs or PCBs with packaged ICs are also needed for these connections as well as metal casings for thermal management [31]. Thus, assembly is still complex and potentially costly in production compared with today’s packaged and PCB-soldered transceivers.
In this article, current approaches toward front-end IC integration for wireless gigabit per second and beyond have been discussed (Table 1). So far, several fundamental architecture concepts, including homodyne, heterodyne, multichannel, and polar approaches, have been demonstrated. A wide range of technologies are used for IC integration, including CMOS, SiGe, InGaAs, and InP. We can observe that the performance in different areas notably depends on technology choice, while very high data rates have been achieved in all of them. Nevertheless, all demonstrations shown so far still require more research and development for a fully integrated transceiver module that is ready for real-world applications. The remaining challenges include power dissipation reduction for improved efficiency, low-phase-noise reference oscillator integration, and improved packaging technologies with less complexity for mass production.
Table 1. A comparison of integrated transceiver demonstration experiments.
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Digital Object Identifier 10.1109/MMM.2023.3277360