Carsten Markgraf, Luca Gacy, Samuel Leitenmaier, Daniel Lengerer, Benjamin Schwartz, David W. Gao
©SHUTTERSTOCK.COM/DAVID ACOSTA ALLELY
As the electric drive finds its way progressively into important industry sectors like mobility, transportation, agriculture, production, and supporting services, it becomes increasingly important to have individually optimized technical solutions for the manifold applications. Therefore, a high number of engineers with interdisciplinary competencies will be needed soon to comply with the demand of the worldwide markets. A key component for an often-used variant of the electric drivetrain is the full-bridge inverter, which is subject to a wide spectrum of different requirements. In 2021, the University of Denver (DU), started a cooperation with the University of Applied Sciences Augsburg (UASA) to develop a full-bridge inverter for an autonomous, electrical Formula Student race car, using four permanent magnet synchronous machines as an all-wheel drive. To improve the performance of the race car, the inverter must be lightweight, package optimized, electromagnetic compatibility compliant, safe, and reliable when it distributes a maximum of 80 kW instantaneous power from the battery at a voltage between 420 V and 600 V individually to the four wheels. This article documents the inverter development process using silicon carbide MOSFET power modules, with the goal of using future results in the race car and the knowledge transfer for the education of engineering students. This transatlantic partnership between DU and UASA also serves as a success story for intercontinental collaborative development based on modern communication and decentralized development techniques.
Inverters are widely used in a variety of applications, including solar power systems, electric vehicles, and industrial motor drives. The development of inverters is an ongoing process, and there are several trends and advancements in the field.
One trend in inverter development is the use of new and more efficient power semiconductor devices. Silicon carbide (SiC) and gallium nitride are two such devices that are being used to improve inverter efficiency and reduce losses. These devices have lower resistance and can operate at higher temperatures than traditional silicon-based devices.
Another trend is the use of advanced control algorithms to improve inverter performance. These algorithms can optimize the inverter’s output based on various factors, such as load conditions, input voltage, switching frequency, and temperature. Increasing the input voltage leads to a reduction of the current and, therefore, the dissipative losses at the same power level. In addition, new control techniques are being developed to improve the reliability and stability of the inverter in challenging environments.
There is also ongoing research into new topologies and architectures for inverters, such as multilevel and modular inverters. These designs can improve the quality of the ac output, reducing the sinusoidal overharmonics and the related losses, as well as disturbing effects like noise and torque ripple generated in the connected electric machine. This allows systems to be more integrated and compact, which leads to more flexibility related to the package situation.
Overall, the current state of inverter development is focused on improving efficiency, reliability, and performance while also reducing cost and size. With the continued growth of renewable energy sources and electric transportation, inverters will continue to play an essential role in the power electronics industry.
A well-known competition to apply such an inverter technology is the Formula Student Electric (FSE), which is described in the next paragraph. It allows the students to develop their own drivetrain and test it to the very limits while competing against other teams. The current drivetrain system of the University of Applied Sciences Augsburg (UASA) is based on four inverters with insulated-gate bipolar transistors (IGBTs) and a switching frequency of 8 kHz. It is connected to permanent magnet synchronous machines (PMSMs) connected to each wheel and has a comparably high undamped weight with a disadvantageous package. To improve these points, a new inverter design was developed in this project and tested in an integrated manner. The development process and its outcome are described in the following chapters with a conclusion presented at the end of this article.
FSE is an international design competition for students to supplement their studies with hands-on experience. The goal is to develop an electric, partially autonomous, race car prototype. The competition challenges students to gain intensive experience in design and development while considering the economic aspects of the automotive industry in the form of a cost breakdown and a fictitious business plan at the same time. The result is evaluated by a jury consisting of experts from the motorsport, automotive, and supplier industries.
Every year, numerous competitions are held around the world in which teams from different universities compete against each other in the various disciplines. The Formula Student Germany is held annually at the Hockenheimring, where over 100 teams, some of them international, take part.
There are two classes: Formula Student Combustion and FSE. The Formula Student Driverless class has been replaced by the Driverless Cup since the 2022 season.
For the development of complex systems like a three-phase inverter with focus on package and weight optimization while still complying to numerous other requirements, it is necessary to define an appropriate work breakdown structure. In this specific case it involves interdisciplinary cooperation between experts for hardware and software development, mechanical and thermal design, as well as integration and testing, with challenges related to electromagnetic compatibility and heat dissipation. This project shows the successful setup of an international team based on a partnership between the University of Denver (Colorado/USA; DU) and the UASA (Bavaria/Germany).
The drivetrain of the existing Formula Student race car consists of a high-voltage (HV) battery (about 428 V–600 V) that holds the necessary energy to run the electric motors for about 22 km, one inverter per motor, to generate the required phase voltages and the desired torque at each wheel individually. The battery is air-cooled, the inverters and motors are water-cooled. All components are schematically shown in Figure 1.
Figure 1. Drivetrain of the FSE race car from StarkStrom Augsburg e.V.
The details about the three main components (HV battery, inverter, and electric motors), shown in Figure 2, that are implemented in the current race car are presented in the following subsections. They are used as a basis for the definition of the new inverter requirements for this project.
Figure 2. Main components: (a) HV battery, (b) inverter, and (c) motor. Battery parameters: Maximum voltage: 600 V; energy:7.5 kWh; maximum charging current: 120 A (for maximum 3 s); maximum continuous discharge current: 120 A. Major inverter characteristics: Input dc bus voltage: 250 Vdc–720 Vdc; intermediate circuit capacity: 75 µF per inverter; switching frequency: 8 kHz; nominal output power: 26 kVA; nominal output current: 43 A; maximum output current: 105 A; volume: 241 × 339 × 183 mm; weight: 11 kg. Motor parameters: Nominal voltage: 350 V; nominal current: 41 ARMS arms; maximum current: 105 A; nominal torque: 9.8 Nm; maximum torque: 21 Nm; nominal revolutions: 13,000 rpm; maximum revolutions: 20,000 rpm; quadrature axis inductance: 0.12 mH; direct axis inductance: 0.24 mH.
The HV battery, as shown in Figure 2(a), is completely self-developed by the racing team. It consists of 12 segments, each having a maximum voltage of 50 V, resulting in a maximum voltage of the battery of 600 V when it is fully charged. Cylindrical lithium-ion rechargeable cells are used as a basis (in total 864). The energy of the battery is designed for the longest distance of the competition. It must be driven in the endurance discipline where the race car must operate 22 km at its dynamic limits. About 7 kWh–7.5 kWh are needed for the actual car design, considering that kinetic energy can be transformed and fed back into the rechargeable battery in braking situations, using the motors in generator mode.
For safety reasons the battery has its own, also self-developed, battery management system that monitors the individual cell voltages and temperatures at different locations within the segments. The HV and low-voltage (LV) systems must be fully galvanically separate from each other. An insulation monitoring device measures the resistance between the systems and allows the accumulator isolation relays (AIRs) to be closed only if all of the monitored signals are in their expected range. In case of a detected failure, the AIRs can disconnect the HV battery at both poles from the rest of the car.
The current inverters, as shown in Figure 2(b), are a part of a so-called “Formula Student Kit,” which consists of the four inverters and four PMSMs from the company AMKmotion. This industrial grade inverter is reliable and relatively easy to use, but relatively big and heavy. The power modules are built using IGBT modules. For the measurement of the rotor angle, it has different position feedback interfaces like an EnDat encoder that is used in the race car. Integrated safety features—like software-based overcurrent protection; monitoring of motor, IGBT module, and cooling plate temperature; and monitoring of the Controller Area Network (CAN) bus communication and of the encoder signal quality—are used for derating and safety functions to protect the car and its driver. A water-cooling circuit is used to transfer the dissipated heat to the cooling radiators. The acceleration pedal signal is used to derive a desired torque generating current that is the input for microcontroller-based closed-loop current control. Field weakening techniques are applied to extend the speed range. The inverters are the focus of this project, with the goal to achieve a lower weight and volume while keeping the power performance at the same level.
The motors are three-phase PMSMs with 10 poles, equipped with an EnDat encoder for rotor position measurement. The windings are connected in delta circuit. These motors will also be used for the integration with the new inverter design, see Figure 2(c).
The requirements for the inverter are derived from the current drivetrain of the race car, as well as additional features that are defined by the developers. Table 1 shows the summary of basic requirements for this project.
Table 1. General requirements.
These requirements are meant to be taken as high level for the fully integrated system.
In general, an inverter consists of the components shown in Figure 3, which can be grouped into the power stage, the driver stage, and control/logic hardware. The power stage contains three half-bridges, which generate the desired voltages of the three phases from the dc-link voltage by means of pulse width modulation (PWM); the dc-link capacitance between the battery and the power module is not shown. The gate drivers are located on the driver stage and generate the gate signals for the power switches from the PWM signals of the processing system. In addition, the gate drivers contain a galvanic isolation between the low voltage of the logic hardware and the high voltage of the drivetrain according to the FSE rules. The control logic includes the interfaces to the motor encoders, the race car, and the current and temperature sensors.
Figure 3. Exemplary structure of an inverter with an HV battery and electric three-phase motor.
For this intense application, WolfSpeed SiC MOSFETs are used in the new inverter system. These will play a large role in the future for high-power electric vehicles given their ability to handle high voltages with a very high efficiency in a physical form factor being more compact in size, as well as having lower energy losses when compared to alternatives, such as IGBTs. To use these SiC MOSFETs, two main components need to work together: the first is the gate driver, with the second being a power module.
The voltage of the PWM signal generated from the control module is insufficient to drive the SiC MOSFETs, so the UCC20520 gate driver (Figure 4) is used to amplify the desired signal to the voltage the MOSFETs operate at. The UCC205020 along with the power supplies used for the amplified signal are galvanically isolated to ensure the low power system is protected in case of a failure on the high voltage side. There is a control pin for the main controller to ensure power is disabled when needed as a safety function when there is a failure. Using a variable resistor, the dead time can also be tuned for an optimal system to prevent temporary short-circuit situations.
Figure 4. Block diagram function of UCC20520 gate driver integrated circuit. Pin 6 is the dead-time pin. It can be set to ground for a dead time of roughly 15 ns or use a variable resistor tied to ground to modify it to the desired time.
This dead time defines the small-time window where both MOSFETs in each half-bridge of the three-phase system are off, preventing any chance of shoot through where the voltage supply would be connected directly to ground causing a short. There is a loss in efficiency the larger the dead time is, but below a certain threshold, shoot through can occur. The WolfSpeed Power Module used for this project is a full-bridge device. Using three half-bridge gate drivers, the three-phase output voltages, with each phase offset by 120 degrees, is electrically generated. Using a multilayer printed circuit board (PCB) or copper traces with large ounces, it is possible to design compact systems that can handle the required current load for the traction motor. A dc-link capacitor is placed in parallel with the battery, which is needed for load balancing, as well as to protect the battery from voltage spikes due to parasitic inductances and switching behavior. Using encoders on the rotors, current sensors, and temperature sensors, the system can function as a closed-loop system.
With these two systems of the gate driver and power module, shown in Figure 5(a) and 5(b), the vehicle can quickly and efficiently produce the power at the wheels that the controller board desires, allowing for faster response times and better control of the system.
Figure 5. (a) Populated PCB for gate driver module. (b) Populated power stage module. (c) Controller board for the new inverter.
One of the main goals of this architecture is to be capable of running two field-oriented control algorithms in parallel. The requirements are derived from Table 1.
Most of the off-chip hardware requirements are already given by the current electrical system of the race car. Furthermore, a big advantage is that most of these requirements would also fit common automotive systems. First, the supply voltage is given with a nominal voltage of 24 V from the LV battery, with an operating range of from 21 V to 29.4 V. Therefore, a voltage regulation circuit is needed, as common integrated circuits use a supply voltage from 1.8 V to 5 V and not 24 V. As the commands for the inverter will be received from the main electronic control unit over a CAN bus, an additional circuit for this interface, that operates at 3.3-V input–output (IO) voltage and 5-V bus voltage, is also required. To use the current motors an EnDat interface is needed to receive the current motor position. As the field-oriented control (FoC) needs the current measurement of each phase and additional measurements for various temperatures, an analog-to-digital converter (ADC) circuit is required that may be used with a digital interface or directly on the field-programmable gate array (FPGA). Finally, the connection for the system on module, described in the following chapter, is needed. The main power supply therefore shall be between 3.3 V and 5 V, the IO Voltage can be 1.8 V, 2.5 V, or 3.3 V. As an additional requirement that does not result from electronic functionality, the hardware should be designed in a way that the integration becomes easy. The off-chip hardware, as shown in Figure 5(c), builds the interface to the gate-driving stage and the power stage.
The architecture on the FPGA is divided into small modules that can be seen in the structural overview in Figure 6. Starting with the main part, the ZYNQ7 Processing System is the connection from the FPGA to the processing system. For configuration, all necessary and possible hard-cores for the processing system are activated, the clock settings are configured, and the connection and controlling of the Zynq system bus that’s called Advanced eXtensible Interface (AXI) is activated. For this architecture, the following hard-cores are used: ENET0, SD0, UART0, CAN0, CAN1.
Figure 6. FPGA modules.
The other used peripherals are integrated as soft-cores and connected over the system internal AXI bus. These modules are connected and controlled: the endat22_0 and endat22_1 (single channel ENDAT peripheral each), the ncd98011_interface (a 12 channel ADC-peripheral) and the generated intellectual property core (IP-core) from a MATLAB® code generation over M00_AXI. To control more than one AXI slave, an AXI Interconnect is required. The AXI Interconnect acts as a multiplexer for all connected slave modules to connect to the AXI master, the ZYNQ7 Processing System.
The low-level software can be implemented either as a bare-metal C/C++ application, as a C/C++ application for an embedded Linux system, or as an application for a symmetric multiprocessing/asymmetric multiprocessing–embedded Linux system together with a real-time operating system, FreeRTOS. The Zynq7020 has two cores, so symmetric multiprocessing (SMP) or asymmetric multiprocessing (AMP) have potential for the final implementation. SMP contains two or more cores, where all cores are connected to same memory and have access to all IO devices. With AMP, one core is assigned as a master processor and runs the actual operating system tasks, and the other cores are running all time-critical tasks and get managed by the master processor. Within this work, the SMP is selected because it is simpler to develop, it has enough capability, and the research is not focusing on this as there is an already-existing system. A Linux system with the preemptive real-time patch running on an ARM device with 666 MHz within the Zynq system on chip is used.
As the PWM is center-aligned for this motor control application, it is necessary to sample the phase currents and the motor position in the center of each switching-cycle. Therefore, a maximum calculation time, Tcal, for corresponding calculations for the FoC is given. Based on the timing values, a control scheduler representing the timing behavior of the architecture is designed. Based on these results and a Tsw of 125 µs for 8 kHz, the ADC can be sampled 250 times; therefore, the 125th sample of each cycle is used. The motor position can be sampled seven times. Therefore, the fourth sample of each cycle is used. The design of this control scheduler is shown in Figure 7. Based on the Free Running mode, the sampling and command pipeline is developed on the base of the actual PWM-switching frequency of 8 kHz. Within this time slot the, FoC algorithm needs to provide the next commands for the PWM.
Figure 7. FoC control scheduler timing.
The custom interrupt from the FPGA is later used to start the FoC calculations in the correct timing. Before this was narrowed down, some software tests needed to be done to guarantee that the FoC calculations are completed before Tcal is over.
The hardware/software codesign with MATLAB®-Simulink helps to implement advanced computational systems quickly. The base FPGA design is included with the MATLAB® hardware description language coder toolbox and extended with the logic from the FPGA part of the Simulink model. The rest of the algorithms are implemented in Simulink and integrated as a compiled executable because of the embedded coder toolbox. The whole workflow guarantees a flexible way of moving algorithms from the processing system to the programmable logic rapidly and without a lot of effort.
To implement the space vector modulation, the measured phase currents are first converted into the rotor-related d/q coordinate system using the Clarke and Park transformation. At constant torque and speed, the currents Id and Iq are uniform controllable variables, which are then compared with the set point values by means of a usual controller structure. The control difference serves as input for proportional integral controllers, and their output then generates a voltage vector for the d- and q-axes. After a subsequent inverse Park transformation into the stator coordinate frame, the duty cycles for the three half-bridges—U, V, and W of the power stage—are calculated by the space vector modulation.
A simulation environment was set up with MATLAB®-Simulink to test the developed control algorithm together with a digital twin of its interfacing environment. This allowed control parameters to be found and optimized, from which the parameters could finally be refined on the real test bench.
The virtual simulation environment contains a motor model to test the space vector modulation and the FoC algorithm. In the future, the model could be refined by, for example, mapping and integrating the power stage and battery. Currently, these components are ideal in the simulation.
To properly cool the power modules and to avoid the risk of insufficient cooling in an air-cooled environment, cooling blocks in a water loop remove heat from the inverter system. Through four separate iterations, improvements were made in heat transfer effectiveness, realistic assembly, and maintenance access, and construction viability. Due to supply and material shortages, additional design changes were made to allow production to move forward.
The initial designs aimed at producing cooling blocks with a minimal footprint, only covering the power modules. Two alternatives were theorized: a single aluminum block with copper tubing inserted, or an aluminum assembly between two identical halves with screws to secure them. One-half–inch diameter tubing was determined to fit U.S. standard tubing sizes.
The second iteration of the aluminum assembly design included more material for the screws to clamp to, as well as threaded ports to be compatible with existing tubing systems. Additionally, 2-mm radii were cut around the outer edges for realistic machining.
From thermal simulations run in Solidworks, it was determined that the thermal transfer capabilities of the previous iterations were insufficient for the system. Several changes addressed this problem.
The Aluminum 6061 theorized for the final version offers a 189% increase in thermal conductivity over the initial version, at 167 (W/m K). Additionally, simulations in Solidworks influenced square channels with pins to dramatically increase heat transfer by creating greater turbulence. To address the attaching of square channels to the rest of the system, panels were added to the ends of the block halves. According to the Solidworks flow simulations, as shown in Figure 8, these modifications add up to a 339.7% increase in turbulence through the system compared to the initial block.
Figure 8. Interior of cooling blocks showing (a) pins to increase dissipation surface and (b) water-flow simulation.
These blocks are intended to run in a water loop propelled by a 12-V dc pump with 5-GPM capacity up to 60 PSI, and all simulations were run with these metrics included.
Over a two-week period in the summer of 2022, an in-person collaboration between DU and UASA was able to occur. This allowed the integration and testing of the previously described systems.
Once the final assembly of the PCBs took place, the testing of each phase was conducted. Powering only a single phase at a time allowed for troubleshooting of potential problems to be made easier. After optimizing resistor and capacitor values, each phase was fully operational. Using an oscilloscope connected to a laptop, the data was gathered and saved through MATLAB® in csv files to be further analyzed, as shown in Figure 9. Once each phase had been tested individually with a function generator, the connection between the controller board and gate driver was tested. With that, the testing of the two systems combined could be conducted successfully.
Figure 9. Initial hardware and software integration without any load.
The custom wire connectors were assembled and the three phases from the controller board were connected to the gate driver.
The switching behavior of the SiC MOSFET was measured. The damped oscillation after switching the MOSFET on, results from the parasitic inductance together with the gate capacitance. This can be optimized with an additional snubber circuitry to reduce the peak voltage for the extension of the lifetime of the MOSFET.
After testing each phase and all three phases with no load, it was time to test it with a resistive load. Using a thermal camera, the system was diagnosed for hot spots or potential issues, as shown in Figure 10. This marked a successful test of each single phase with low dc-link voltage, but high current. After finishing the integrated testing, it was concluded that the design provides a solid baseline for further development and final integration into the race car.
Figure 10. Identification of thermal hotspots using a thermal camera.
This article documents the international collaborative research and development work involving faculty and students with the goal to build an optimized inverter for the electric drivetrain of an autonomous Formula Student race car. We focused on developing full-bridge inverters for the vehicle, using four PMSMs for an all-wheel drive. In particular, we aimed on using state-of-the-art SiC MOSFET power modules, with the goal of reducing system cost and size while improving efficiency, reliability, and performance. A common hardware and software integration was achieved successfully at DU. The partnership and preliminary work of the DU and UASA students will help promote future international exchange activities regarding research in electromobility, autonomous driving, and smart cities for enhancing the education of engineering students. We plan to address the identified challenges and conduct further closed-loop testing on a traction motor test bench in our future iterations of this educational student project. This is the result of a positive example for intercontinental collaboration between enthusiastic engineering students.
We acknowledge the funding support of the University of Denver Internationalization grant.
StarkStrom Augsburg e.V. [Online] . Available: https://starkstrom-augsburg.de/ueber-uns/formula-student/
X. Wang, N. Liu, and R. Na, “Simulation of PMSM field-oriented control based on SVPWM,” in Proc. IEEE Veh. Power Propulsion Conf., Dearborn, MI, USA, 2009, pp. 1465–1469, doi: 10.1109/VPPC.2009.5289523.
“PMSM field-oriented control,” MathWorks, Natick, MA, USA. [Online] . Available: https://www.mathworks.com/help/sps/ref/pmsmfieldorientedcontrol.html
F. Amin, E. Sulaiman, and H. Soomro, “Field oriented control principles for synchronous motor,” Int. J. Mech. Eng. Robot. Res., vol. 8, pp. 284–288, Mar. 2019, doi: 10.18178/ijmerr.8.2.284-288.
Carsten Markgraf (carsten.markgraf@hs-augsburg.de) is with the Faculty of Electrical Engineering, Technical University of Applied Sciences Augsburg, 86343, Augsburg/Bavaria, Germany.
Luca Gacy (luca.gacy@du.edu) is with the School of Engineering and Computer Science, University of Denver, Denver, CO 80208 USA.
Samuel Leitenmaier (samuel.leitenmaier@hs-augsburg.de) is with the Faculty of Electrical Engineering, Technical University of Applied Sciences Augsburg, 86199, Augsburg/Bavaria, Germany.
Daniel Lengerer (daniel.lengerer@hs-augsburg.de) is with the Faculty of Electrical Engineering, Technical University of Applied Sciences Augsburg, 86161, Augsburg/Bavaria, Germany.
Benjamin Schwartz (benjamin.schwartz@me.com) is with the School of Engineering and Computer Science, University of Denver, Denver, CO 80208 USA.
David W. Gao (david.gao@du.edu) is with the School of Engineering and Computer Science, University of Denver, Denver, CO 80208 USA.
Digital Object Identifier 10.1109/MELE.2023.3264921
2325-5897/23©2023IEEE